[llvm-commits] [llvm] r157894 - /llvm/trunk/lib/Target/X86/X86InstrFMA.td

[Craig Topper]

Author: ctopper
Date: Sat Jun  2 19:30:49 2012
New Revision: 157894

URL: http://llvm.org/viewvc/llvm-project?rev=157894&view=rev
Log:
Add neverHasSideEffects and mayLoad to FMA3 instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFMA.td

Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=157894&r1=157893&r2=157894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Sat Jun  2 19:30:49 2012
@@ -17,6 +17,7 @@
 
 let Constraints = "$src1 = $dst" in {
 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
+let neverHasSideEffects = 1 in {
   def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
            (ins VR128:$src1, VR128:$src2, VR128:$src3),
            !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -35,6 +36,7 @@
            (ins VR256:$src1, VR256:$src2, f256mem:$src3),
            !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
            []>;
+} // neverHasSideEffects = 1
 }
 
 // Intrinsic for 132 pattern
@@ -117,14 +119,17 @@
 let Constraints = "$src1 = $dst" in {
 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
                     RegisterClass RC> {
+let neverHasSideEffects = 1 in {
   def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
            (ins RC:$src1, RC:$src2, RC:$src3),
            !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
            []>;
+  let mayLoad = 1 in
   def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
            (ins RC:$src1, RC:$src2, x86memop:$src3),
            !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
            []>;
+} // neverHasSideEffects = 1
 }
 
 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,