[llvm-commits] [llvm] r157234 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsCondMov.td MipsInstrFPU.td MipsInstrFormats.td MipsInstrInfo.td MipsSubtarget.h

[Benjamin Kramer]

On 22.05.2012, at 05:10, Akira Hatanaka wrote:

> Author: ahatanak
> Date: Mon May 21 22:10:09 2012
> New Revision: 157234
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=157234&view=rev
> Log:
> This patch adds a predicate to existing mips32 and mips64 so that those
> instruction encodings can be excluded during mips16 processing.
> 
> This revision fixes the issue raised by Jim Grosbach.
> 
> bool hasStandardEncoding() const { return !inMips16Mode(); }
> 
> When micromips is added it will be
> 
> bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }
> 
> No additional testing is needed other than to assure that there is no regression
> from this patch.
> 
> Patch by Reed Kotler.
> 
> Modified:
>    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
>    llvm/trunk/lib/Target/Mips/MipsCondMov.td
>    llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
>    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>    llvm/trunk/lib/Target/Mips/MipsSubtarget.h
> 
[…]
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=157234&r1=157233&r2=157234&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon May 21 22:10:09 2012
> @@ -117,15 +117,15 @@
> multiclass FFR1_W_M<bits<6> funct, string opstr> {
>   def _S   : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
>   def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
> -             Requires<[NotFP64bit]>;
> +             Requires<[NotFP64bit, HasStandardEncoding]>;
>   def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
> -             Requires<[IsFP64bit]> {
> +             Requires<[IsFP64bit, HasStandardEncoding]> {
>     let DecoderNamespace = "Mips64";
>   }
> }
> 
> // Instructions that convert an FP value to 64-bit fixed point.
> -let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
> +let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64" in
> multiclass FFR1_L_M<bits<6> funct, string opstr> {
>   def _S   : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
>   def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
> @@ -135,9 +135,9 @@
> multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
>   def _S   : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
>   def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
> -             Requires<[NotFP64bit]>;
> +             Requires<[NotFP64bit, HasStandardEncoding]>;
>   def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
> -             Requires<[IsFP64bit]> {
> +             Requires<[IsFP64bit, HasStandardEncoding]> {
>     let DecoderNamespace = "Mips64";
>   }
> }
> @@ -146,9 +146,9 @@
>   let isCommutable = isComm in {
>   def _S   : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
>   def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
> -             Requires<[NotFP64bit]>;
> +             Requires<[NotFP64bit, HasStandardEncoding]>;
>   def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
> -             Requires<[IsFP64bit]> {
> +             Requires<[IsFP64bit, HasStandardEncoding]> {
>     let DecoderNamespace = "Mips64";
>   }
> }
> @@ -185,13 +185,13 @@
> def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
> def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
> 
> -let Predicates = [NotFP64bit] in {
> +let Predicates = [NotFP64bit, HasStandardEncoding] in {
>   def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
>   def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
>   def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
> }
> 
> -let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
> +let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64" in {
>  def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
>  def CVT_S_L   : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
>  def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
> @@ -199,7 +199,7 @@
>  def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
> }
> 
> -let Predicates = [NoNaNsFPMath] in {
> +let Predicates = [NoNaNsFPMath, HasStandardEncoding] in {
>   defm FABS    : FFR1P_M<0x5, "abs",  fabs>;
>   defm FNEG    : FFR1P_M<0x7, "neg",  fneg>;
> }
> @@ -242,14 +242,14 @@
> 
> def FMOV_S   : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
> def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
> -               Requires<[NotFP64bit]>;
> +               Requires<[NotFP64bit, HasStandardEncoding]>;
> def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
> -               Requires<[IsFP64bit]> {
> +               Requires<[IsFP64bit, HasStandardEncoding]> {
>   let DecoderNamespace = "Mips64";
> }
> 
> /// Floating Point Memory Instructions
> -let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
> +let Predicates = [IsN64, HasStandardEncoding], DecoderNamespace = "Mips64" in {
>   def LWC1_P8   : FPLoad<0x31, "lwc1", FGR32, mem64>;
>   def SWC1_P8   : FPStore<0x39, "swc1", FGR32, mem64>;
>   def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
> @@ -260,41 +260,42 @@
>   }
> }
> 
> -let Predicates = [NotN64] in {
> +let Predicates = [NotN64, HasStandardEncoding] in {
>   def LWC1   : FPLoad<0x31, "lwc1", FGR32, mem>;
>   def SWC1   : FPStore<0x39, "swc1", FGR32, mem>;
> }
> 
> -let Predicates = [NotN64, HasMips64], DecoderNamespace = "Mips64" in {
> +let Predicates = [NotN64, HasMips64, HasStandardEncoding],
> +    DecoderNamespace = "Mips64" in {
>   def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
>   def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
> }
> 
> -let Predicates = [NotN64, NotMips64] in {
> +let Predicates = [NotN64, NotMips64, HasStandardEncoding] in {
>   def LDC1   : FPLoad<0x35, "ldc1", AFGR64, mem>;
>   def SDC1   : FPStore<0x3d, "sdc1", AFGR64, mem>;
> }

In the (dis)assembler "HasStandardEncoding" implies "FeatureMips64" so this predicate list contains a contradiction (NotMips64 && Mips64). You probably want something like AssemblerPredicate<"!FeatureMips16"> for HasStandardEncoding.

- Ben