[llvm-commits] [llvm] r156697 - in /llvm/trunk/test/CodeGen/Mips: 2010-07-20-Switch.ll alloca.ll analyzebranch.ll atomic.ll cmov.ll cprestore.ll eh.ll gprestore.ll inlineasmmemop.ll internalfunc.ll largeimmprinting.ll o32_cc_byval.ll tls.ll
Akira Hatanaka
ahatanaka at mips.com
Fri May 11 20:25:16 PDT 2012
Author: ahatanak
Date: Fri May 11 22:25:16 2012
New Revision: 156697
URL: http://llvm.org/viewvc/llvm-project?rev=156697&view=rev
Log:
Fix test cases.
Modified:
llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
llvm/trunk/test/CodeGen/Mips/alloca.ll
llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
llvm/trunk/test/CodeGen/Mips/atomic.ll
llvm/trunk/test/CodeGen/Mips/cmov.ll
llvm/trunk/test/CodeGen/Mips/cprestore.ll
llvm/trunk/test/CodeGen/Mips/eh.ll
llvm/trunk/test/CodeGen/Mips/gprestore.ll
llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
llvm/trunk/test/CodeGen/Mips/internalfunc.ll
llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
llvm/trunk/test/CodeGen/Mips/tls.ll
Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll Fri May 11 22:25:16 2012
@@ -11,16 +11,19 @@
; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0)
-; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
-; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
-; PIC-O32: addu $[[R1:[0-9]+]], ${{[0-9]+}}, $gp
-; PIC-O32: jr $[[R1]]
-; PIC-N64: daddiu $[[R2:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(main)))
+; PIC-O32: addiu $[[R1:[0-9]+]], $[[R0]], %lo($JTI0_0)
+; PIC-O32: sll $[[R2:[0-9]+]], ${{[0-9]+}}, 2
+; PIC-O32: addu $[[R3:[0-9]+]], $[[R2]], $[[R1]]
+; PIC-O32: lw $[[R4:[0-9]+]], 0($[[R3]])
+; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
+; PIC-O32: jr $[[R5]]
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
-; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0)
-; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3
-; PIC-N64: daddu $[[R1:[0-9]+]], ${{[0-9]+}}, $[[R2]]
-; PIC-N64: jr $[[R1]]
+; PIC-N64: daddiu $[[R1:[0-9]+]], $[[R0]], %got_ofst($JTI0_0)
+; PIC-N64: dsll $[[R2:[0-9]+]], ${{[0-9]+}}, 3
+; PIC-N64: daddu $[[R3:[0-9]+]], $[[R2:[0-9]+]], $[[R1]]
+; PIC-N64: ld $[[R4:[0-9]+]], 0($[[R3]])
+; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
+; PIC-N64: jr $[[R5]]
switch i32 %0, label %bb4 [
i32 0, label %bb5
i32 1, label %bb1
Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/alloca.ll Fri May 11 22:25:16 2012
@@ -8,7 +8,7 @@
; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
; CHECK: addu $sp, $zero, $[[T2]]
; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
-; CHECK: lw $[[T4:[0-9]+]], %call16(foo)($gp)
+; CHECK: lw $[[T4:[0-9]+]], %call16(foo)
; CHECK: addu $25, $zero, $[[T4]]
; CHECK: addu $4, $zero, $[[T1]]
; CHECK: jalr $25
@@ -31,14 +31,10 @@
define i32 @alloca2(i32 %size) nounwind {
entry:
-; dynamic allocated stack area and $gp restore slot have the same offsets
-; relative to $sp.
-;
; CHECK: alloca2
-; CHECK: .cprestore [[OFF:[0-9]+]]
-; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
+; CHECK: subu $[[T0:[0-9]+]], $sp
; CHECK: addu $sp, $zero, $[[T0]]
-; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
+; CHECK: addiu $[[T1:[0-9]+]], $sp
%tmp1 = alloca i8, i32 %size, align 4
%0 = bitcast i8* %tmp1 to i32*
Modified: llvm/trunk/test/CodeGen/Mips/analyzebranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/analyzebranch.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/analyzebranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/analyzebranch.ll Fri May 11 22:25:16 2012
@@ -2,9 +2,8 @@
define double @foo(double %a, double %b) nounwind readnone {
entry:
-; CHECK: bc1f $BB0_2
+; CHECK: bc1f $BB
; CHECK: nop
-; CHECK: # BB#1:
%cmp = fcmp ogt double %a, 0.000000e+00
br i1 %cmp, label %if.end6, label %if.else
@@ -26,9 +25,8 @@
define void @f1(float %f) nounwind {
entry:
-; CHECK: bc1f $BB1_1
+; CHECK: bc1f $BB
; CHECK: nop
-; CHECK: # BB#2:
%cmp = fcmp une float %f, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/atomic.ll Fri May 11 22:25:16 2012
@@ -8,7 +8,7 @@
ret i32 %0
; CHECK: AtomicLoadAdd32:
-; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(x)
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
@@ -22,7 +22,7 @@
ret i32 %0
; CHECK: AtomicLoadNand32:
-; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(x)
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4
@@ -40,7 +40,7 @@
ret i32 %0
; CHECK: AtomicSwap32:
-; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(x)
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll ${{[0-9]+}}, 0($[[R0]])
; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
@@ -56,7 +56,7 @@
ret i32 %0
; CHECK: AtomicCmpSwap32:
-; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(x)
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $2, 0($[[R0]])
; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
@@ -75,7 +75,7 @@
ret i8 %0
; CHECK: AtomicLoadAdd8:
-; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(y)
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
@@ -106,7 +106,7 @@
ret i8 %0
; CHECK: AtomicLoadSub8:
-; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(y)
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
@@ -137,7 +137,7 @@
ret i8 %0
; CHECK: AtomicLoadNand8:
-; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(y)
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
@@ -169,7 +169,7 @@
ret i8 %0
; CHECK: AtomicSwap8:
-; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(y)
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
@@ -198,7 +198,7 @@
ret i8 %0
; CHECK: AtomicCmpSwap8:
-; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(y)
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
Modified: llvm/trunk/test/CodeGen/Mips/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cmov.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cmov.ll Fri May 11 22:25:16 2012
@@ -5,8 +5,8 @@
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
-; O32: lw ${{[0-9]+}}, %got(i3)($gp)
-; O32: addiu ${{[0-9]+}}, $gp, %got(i1)
+; O32: lw ${{[0-9]+}}, %got(i3)
+; O32: addiu ${{[0-9]+}}, ${{[a-z0-9]+}}, %got(i1)
; N64: ld ${{[0-9]+}}, %got_disp(i3)
; N64: daddiu ${{[0-9]+}}, ${{[0-9]+}}, %got_disp(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
@@ -21,8 +21,8 @@
@d = global i32 0, align 4
; O32: cmov2:
-; O32: addiu $[[R1:[0-9]+]], $gp, %got(d)
-; O32: addiu $[[R0:[0-9]+]], $gp, %got(c)
+; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
+; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
; N64: cmov2:
; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
Modified: llvm/trunk/test/CodeGen/Mips/cprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cprestore.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cprestore.ll Fri May 11 22:25:16 2012
@@ -1,4 +1,6 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; DISABLE: llc -march=mipsel < %s | FileCheck %s
+; RUN: false
+; XFAIL: *
; CHECK: .set macro
; CHECK: .set at
Modified: llvm/trunk/test/CodeGen/Mips/eh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/eh.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/eh.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/eh.ll Fri May 11 22:25:16 2012
@@ -15,7 +15,6 @@
; CHECK-EB: .cfi_offset 53, -8
; CHECK-EB: .cfi_offset 52, -4
; CHECK-EL: .cfi_offset 31, -12
-; CHECK-EL: .cprestore
%exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
%0 = bitcast i8* %exception to double*
@@ -25,7 +24,6 @@
lpad: ; preds = %entry
; CHECK-EL: # %lpad
-; CHECK-EL: lw $gp
; CHECK-EL: bne $5
%exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
Modified: llvm/trunk/test/CodeGen/Mips/gprestore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/gprestore.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/gprestore.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/gprestore.ll Fri May 11 22:25:16 2012
@@ -1,4 +1,6 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; DISABLE: llc -march=mips < %s | FileCheck %s
+; RUN: false
+; XFAIL: *
@p = external global i32
@q = external global i32
Modified: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Fri May 11 22:25:16 2012
@@ -11,7 +11,7 @@
; CHECK: #APP
; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
; CHECK: #NO_APP
-; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
+; CHECK: lw $[[T1:[0-9]+]], %got(g1)
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4
Modified: llvm/trunk/test/CodeGen/Mips/internalfunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/internalfunc.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/internalfunc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/internalfunc.ll Fri May 11 22:25:16 2012
@@ -6,7 +6,7 @@
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
entry:
-; CHECK: lw $[[R0:[0-9]+]], %got(f2)($gp)
+; CHECK: lw $[[R0:[0-9]+]], %got(f2)
; CHECK: addiu $25, $[[R0]], %lo(f2)
tail call fastcc void @f2()
ret i32 0
@@ -14,7 +14,7 @@
define void @caller(i32 %a0, i32 %a1) nounwind {
entry:
-; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)
; CHECK: lw $25, %lo(caller.sf1)($[[R1]])
%tobool = icmp eq i32 %a1, 0
br i1 %tobool, label %if.end, label %if.then
@@ -25,9 +25,9 @@
br label %if.end
if.end: ; preds = %entry, %if.then
-; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp)
+; CHECK: lw $[[R2:[0-9]+]], %got(sf2)
; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
-; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)
; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
%tobool3 = icmp ne i32 %a0, 0
%tmp4 = load void (...)** @gf1, align 4
Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri May 11 22:25:16 2012
@@ -7,9 +7,8 @@
define void @f() nounwind {
entry:
; CHECK: lui $at, 65534
-; CHECK: addiu $at, $at, -24
+; CHECK: addiu $at, $at, -16
; CHECK: addu $sp, $sp, $at
-; CHECK: .cprestore 65536
%agg.tmp = alloca %struct.S1, align 1
%tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Fri May 11 22:25:16 2012
@@ -10,7 +10,7 @@
define void @f1() nounwind {
entry:
-; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp)
+; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)
; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
@@ -43,16 +43,16 @@
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: lw $4, 88($sp)
-; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 72($sp)
-; CHECK: lw $[[R4:[0-9]+]], 76($sp)
-; CHECK: lw $[[R2:[0-9]+]], 68($sp)
-; CHECK: lh $[[R1:[0-9]+]], 66($sp)
-; CHECK: lb $[[R0:[0-9]+]], 64($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: lw $4, 80($sp)
+; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp)
+; CHECK: lw $[[R3:[0-9]+]], 64($sp)
+; CHECK: lw $[[R4:[0-9]+]], 68($sp)
+; CHECK: lw $[[R2:[0-9]+]], 60($sp)
+; CHECK: lh $[[R1:[0-9]+]], 58($sp)
+; CHECK: lb $[[R0:[0-9]+]], 56($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R2]], 24($sp)
@@ -80,13 +80,13 @@
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: sw $5, 60($sp)
-; CHECK: sw $4, 56($sp)
-; CHECK: lw $4, 56($sp)
-; CHECK: lw $[[R0:[0-9]+]], 68($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: sw $4, 48($sp)
+; CHECK: lw $4, 48($sp)
+; CHECK: lw $[[R0:[0-9]+]], 60($sp)
; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@@ -99,13 +99,13 @@
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: sw $5, 60($sp)
-; CHECK: lw $4, 68($sp)
-; CHECK: lw $[[R1:[0-9]+]], 88($sp)
-; CHECK: lb $[[R0:[0-9]+]], 60($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: lw $4, 60($sp)
+; CHECK: lw $[[R1:[0-9]+]], 80($sp)
+; CHECK: lb $[[R0:[0-9]+]], 52($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 24($sp)
Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=156697&r1=156696&r2=156697&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tls.ll Fri May 11 22:25:16 2012
@@ -13,8 +13,9 @@
; CHECK: f1:
-; PIC: lw $25, %call16(__tls_get_addr)($gp)
-; PIC: addiu $4, $gp, %tlsgd(t1)
+; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
+; PIC: lw $25, %call16(__tls_get_addr)($[[R0]])
+; PIC: addiu $4, $[[R0]], %tlsgd(t1)
; PIC: jalr $25
; PIC: lw $2, 0($2)
@@ -35,8 +36,9 @@
; CHECK: f2:
-; PIC: lw $25, %call16(__tls_get_addr)($gp)
-; PIC: addiu $4, $gp, %tlsgd(t2)
+; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
+; PIC: lw $25, %call16(__tls_get_addr)($[[R0]])
+; PIC: addiu $4, $[[R0]], %tlsgd(t2)
; PIC: jalr $25
; PIC: lw $2, 0($2)
@@ -44,9 +46,9 @@
; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
-; STATIC: addiu ${{[a-z0-9]+}}, $[[R0]], %lo(__gnu_local_gp)
+; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATIC: rdhwr $3, $29
-; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp)
+; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]]
; STATIC: lw $2, 0($[[R1]])
}
@@ -57,7 +59,7 @@
entry:
; CHECK: f3:
-; PIC: addiu $4, $gp, %tlsldm(f3.i)
+; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
; PIC: jalr $25
; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2
More information about the llvm-commits
mailing list