[llvm-commits] [llvm] r156634 - in /llvm/trunk: lib/Target/Hexagon/ lib/Target/Hexagon/InstPrinter/ test/CodeGen/Hexagon/

[Brendon Cahoon]

Yea, a very ugly file to commit.  This is a file that we would like/are
planning to be generated using Tablegen.   It's used by our backend to
determine the instructions that allow constant extenders.  Constant
extenders enable some instructions to use 32-bit operands.  For example,
rather than using two instructions to load a global variable (loading the
address and then using an indirect load), we can use the constant extended
version that uses a single load.

-- Brendon

--
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Friday, May 11, 2012 6:12 PM
To: Brendon Cahoon
Cc: llvm-commits at cs.uiuc.edu; Tony Linthicum
Subject: Re: [llvm-commits] [llvm] r156634 - in /llvm/trunk:
lib/Target/Hexagon/ lib/Target/Hexagon/InstPrinter/ test/CodeGen/Hexagon/


On May 11, 2012, at 12:57 PM, Brendon Cahoon <bcahoon at codeaurora.org> wrote:

> +const HexagonConstExtInfo HexagonCExt[] = {
> +  {"PHI", -1, 0, 0, -1},
> +  {"INLINEASM", -1, 0, 0, -1},
> +  {"PROLOG_LABEL", -1, 0, 0, -1},
> +  {"EH_LABEL", -1, 0, 0, -1},
> +  {"GC_LABEL", -1, 0, 0, -1},
> +  {"KILL", -1, 0, 0, -1},
> +  {"EXTRACT_SUBREG", -1, 0, 0, -1},
> +  {"INSERT_SUBREG", -1, 0, 0, -1},
> +  {"IMPLICIT_DEF", -1, 0, 0, -1},
> +  {"SUBREG_TO_REG", -1, 0, 0, -1},
> +  {"COPY_TO_REGCLASS", -1, 0, 0, -1},
> +  {"DBG_VALUE", -1, 0, 0, -1},
> +  {"REG_SEQUENCE", -1, 0, 0, -1},
> +  {"COPY", -1, 0, 0, -1},
> +  {"BUNDLE", -1, 0, 0, -1},
> +  {"ADD64_rr", -1, 0, 0, -1},
> +  {"ADDASL", -1, 0, 0, -1},
> +  {"ADD_ri", 2, -32768, 32767, Hexagon::ADD_rr},
> +  {"ADD_ri_cNotPt", 3, -128, 127, Hexagon::ADD_rr_cNotPt},
> +  {"ADD_ri_cPt", 3, -128, 127, Hexagon::ADD_rr_cPt},
> +  {"ADD_ri_cdnNotPt", 3, -128, 127, Hexagon::ADD_rr_cdnNotPt},
> +  {"ADD_ri_cdnPt", 3, -128, 127, Hexagon::ADD_rr_cdnPt},
> +  {"ADD_rr", -1, 0, 0, -1},
> +  {"ADD_rr_cNotPt", -1, 0, 0, -1},
.
> +  {"ZXTB_cNotPt_V4", -1, 0, 0, -1},
> +  {"ZXTB_cPt_V4", -1, 0, 0, -1},
> +  {"ZXTB_cdnNotPt_V4", -1, 0, 0, -1},
> +  {"ZXTB_cdnPt_V4", -1, 0, 0, -1},
> +  {"ZXTH", -1, 0, 0, -1},
> +  {"ZXTH_cNotPt_V4", -1, 0, 0, -1},
> +  {"ZXTH_cPt_V4", -1, 0, 0, -1},
> +  {"ZXTH_cdnNotPt_V4", -1, 0, 0, -1},
> +  {"ZXTH_cdnPt_V4", -1, 0, 0, -1},
> +  {"fADD64_rr", -1, 0, 0, -1},
> +  {"fADD_rr", -1, 0, 0, -1},
> +  {"fMUL64_rr", -1, 0, 0, -1},
> +  {"fMUL_rr", -1, 0, 0, -1},
> +  {"fSUB64_rr", -1, 0, 0, -1},
> +  {"fSUB_rr", -1, 0, 0, -1},
> +  {"INSTRUCTION_LIST_END", -1, 0, 0, -1}, };


!