[llvm-commits] [llvm] r156599 - in /llvm/trunk: lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/sub-cmp-peephole.ll

[Nick Lewycky]

Manman Ren wrote:
> Author: mren
> Date: Thu May 10 20:30:47 2012
> New Revision: 156599
>
> URL: http://llvm.org/viewvc/llvm-project?rev=156599&view=rev
> Log:
> ARM: peephole optimization to remove cmp instruction
>
> This patch will optimize the following cases:
>    sub r1, r3 | sub r1, imm
>    cmp r3, r1 or cmp r1, r3 | cmp r1, imm
>    bge L1
>
> TO
>    subs r1, r3
>    bge  L1 or ble L1
>
> If the branch instruction can use flag from "sub", then we can replace
> "sub" with "subs" and eliminate the "cmp" instruction.
>
> rdar: 10734411
>
> Added:
>      llvm/trunk/test/CodeGen/ARM/sub-cmp-peephole.ll
> Modified:
>      llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
>      llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>

> +  // There are two possible candidates which can be changed to set CPSR:
> +  // One is MI, the other is a SUB instruction.
> +  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
> +  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
> +  MachineInstr *Sub = NULL;
> +  unsigned SrcReg2 = 0;
> +  if (CmpInstr->getOpcode() == ARM::CMPrr ||
> +      CmpInstr->getOpcode() == ARM::t2CMPrr) {
> +    SrcReg2 = CmpInstr->getOperand(1).getReg();
> +    // MI is not a candidate for CMPrr.
> +    MI = NULL;
> +  } else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
> +    // Conservatively refuse to convert an instruction which isn't in the same
> +    // BB as the comparison.
> +    // For CMPri, we need to check Sub, thus we can't return here.
> +    if(CmpInstr->getOpcode() == ARM::CMPri ||

Space between 'if' and '(' please. See 
http://llvm.org/docs/CodingStandards.html#micro_spaceparen .

> +
> +    // Modify the condition code of operands in OperandsToUpdate.
> +    // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
> +    // be changed from r2>  r1 to r1<  r2, from r2<  r1 to r1>  r2, etc.
> +    for (unsigned i = 0; i<  OperandsToUpdate.size(); i++) {
> +      ARMCC::CondCodes CC = (ARMCC::CondCodes)OperandsToUpdate[i]->getImm();
> +      ARMCC::CondCodes NewCC;
> +      switch(CC) {

And here, space after 'switch'.

Nick

> +      default: break;
> +      case ARMCC::GE: NewCC = ARMCC::LE; break;
> +      case ARMCC::LT: NewCC = ARMCC::GT; break;
> +      case ARMCC::GT: NewCC = ARMCC::LT; break;
> +      case ARMCC::LE: NewCC = ARMCC::GT; break;
> +      }
> +      OperandsToUpdate[i]->setImm(NewCC);
> +    }