[llvm-commits] [PATCH]: PR 12760: Fix incorrect pattern matching of SMMLS instruction

[Meador Inge]

Hi All,

In PR 12760 Mans Rullgard reported an issue (and thoughtfully explained it)
where we are incorrectly producing a 'SMMLS' instruction for the
'(sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm))' pattern.  This will produce incorrect
results if any of the lower 32-bits of the 64-bit multiplication result are set.

As a concrete example consider the following function:

define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
entry:
  %conv4 = zext i32 %a to i64
  %conv1 = sext i32 %b to i64
  %conv2 = sext i32 %c to i64
  %mul = mul nsw i64 %conv2, %conv1
  %shr5 = lshr i64 %mul, 32
  %sub = sub nsw i64 %conv4, %shr5
  %conv3 = trunc i64 %sub to i32
  ret i32 %conv3
}

this currently gets compiled to (llc -march=arm -mcpu=cortex-a8 smml.ll):

_f:
	smmls	r0, r2, r1, r0
	bx	lr

Further consider the case 'f(1, 1, 1)'.  This incorrectly returns 0 when it
should return 1.

The attached patch fixes this be removing the pattern for 'SMMLS'.  The
generated code is now correctly:

_f:
	smmul	r1, r2, r1
	sub	r0, r0, r1
	bx	lr

OK?

(P.S. If it is OK, can someone commit for me?  I don't have write access.)

-- 
# Meador
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