[llvm-commits] [llvm] r156277 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

[Eric Christopher]

Author: echristo
Date: Sun May  6 22:13:16 2012
New Revision: 156277

URL: http://llvm.org/viewvc/llvm-project?rev=156277&view=rev
Log:
When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=156277&r1=156276&r2=156277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Sun May  6 22:13:16 2012
@@ -3054,7 +3054,7 @@
     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
     case 'y': // Same as 'r'. Exists for compatibility.
     case 'r':
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
         return std::make_pair(0U, &Mips::CPURegsRegClass);
       assert(VT == MVT::i64 && "Unexpected type.");
       return std::make_pair(0U, &Mips::CPU64RegsRegClass);