[llvm-commits] [llvm] r156195 - in /llvm/trunk: lib/Target/ARM/Thumb2SizeReduction.cpp test/CodeGen/Thumb2/thumb2-cmn.ll

[Sebastian Pop]

Author: spop
Date: Fri May  4 14:53:56 2012
New Revision: 156195

URL: http://llvm.org/viewvc/llvm-project?rev=156195&view=rev
Log:
Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
    llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=156195&r1=156194&r2=156195&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Fri May  4 14:53:56 2012
@@ -67,6 +67,7 @@
     { ARM::t2BICrr, 0,            ARM::tBIC,     0,   0,    0,   1,  0,0, 1,0 },
     //FIXME: Disable CMN, as CCodes are backwards from compare expectations
     //{ ARM::t2CMNrr, ARM::tCMN,  0,             0,   0,    1,   0,  2,0, 0,0 },
+    { ARM::t2CMNzrr, ARM::tCMNz,  0,             0,   0,    1,   0,  2,0, 0,0 },
     { ARM::t2CMPri, ARM::tCMPi8,  0,             8,   0,    1,   0,  2,0, 0,0 },
     { ARM::t2CMPrr, ARM::tCMPhir, 0,             0,   0,    0,   0,  2,0, 0,1 },
     { ARM::t2EORrr, 0,            ARM::tEOR,     0,   0,    0,   1,  0,0, 1,0 },

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll?rev=156195&r1=156194&r2=156195&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-cmn.ll Fri May  4 14:53:56 2012
@@ -9,7 +9,7 @@
     ret i1 %tmp
 }
 ; CHECK: f1:
-; CHECK: 	cmn.w	r0, r1
+; CHECK: 	cmn	r0, r1
 
 define i1 @f2(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -17,7 +17,7 @@
     ret i1 %tmp
 }
 ; CHECK: f2:
-; CHECK: 	cmn.w	r0, r1
+; CHECK: 	cmn	r0, r1
 
 define i1 @f3(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -25,7 +25,7 @@
     ret i1 %tmp
 }
 ; CHECK: f3:
-; CHECK: 	cmn.w	r0, r1
+; CHECK: 	cmn	r0, r1
 
 define i1 @f4(i32 %a, i32 %b) {
     %nb = sub i32 0, %b
@@ -33,7 +33,7 @@
     ret i1 %tmp
 }
 ; CHECK: f4:
-; CHECK: 	cmn.w	r0, r1
+; CHECK: 	cmn	r0, r1
 
 define i1 @f5(i32 %a, i32 %b) {
     %tmp = shl i32 %b, 5
@@ -73,3 +73,13 @@
 ; CHECK: f8:
 ; CHECK: 	cmn.w	r0, r0, ror #8
 
+
+define void @f9(i32 %a, i32 %b) nounwind optsize {
+  tail call void asm sideeffect "cmn.w     r0, r1", ""() nounwind, !srcloc !0
+  ret void
+}
+
+!0 = metadata !{i32 81}
+
+; CHECK: f9:
+; CHECK: 	cmn.w	r0, r1