[llvm-commits] [llvm] r155618 - in /llvm/trunk/lib/Target/X86: X86.td X86Subtarget.cpp

[Roman Divacky]

Any reason to not enable this on AMD too? ie. on bdver1/bdver2

On Thu, Apr 26, 2012 at 06:40:15AM -0000, Craig Topper wrote:
> Author: ctopper
> Date: Thu Apr 26 01:40:15 2012
> New Revision: 155618
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=155618&view=rev
> Log:
> Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
> 
> Modified:
>     llvm/trunk/lib/Target/X86/X86.td
>     llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/X86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=155618&r1=155617&r2=155618&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86.td (original)
> +++ llvm/trunk/lib/Target/X86/X86.td Thu Apr 26 01:40:15 2012
> @@ -173,21 +173,19 @@
>  // Sandy Bridge
>  // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
>  // rather than a superset.
> -// FIXME: Disabling AVX for now since it's not ready.
> -def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
> +def : Proc<"corei7-avx",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
>                                 FeatureAES, FeatureCLMUL]>;
>  // Ivy Bridge
> -def : Proc<"core-avx-i",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
> +def : Proc<"core-avx-i",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
>                                 FeatureAES, FeatureCLMUL,
>                                 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
>  
>  // Haswell
> -// FIXME: Disabling AVX/AVX2/FMA3 for now since it's not ready.
> -def : Proc<"core-avx2",       [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
> +def : Proc<"core-avx2",       [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,
>                                 FeatureAES, FeatureCLMUL, FeatureRDRAND,
>                                 FeatureF16C, FeatureFSGSBase,
>                                 FeatureMOVBE, FeatureLZCNT, FeatureBMI,
> -                               FeatureBMI2]>;
> +                               FeatureBMI2, FeatureFMA3]>;
>  
>  def : Proc<"k6",              [FeatureMMX]>;
>  def : Proc<"k6-2",            [Feature3DNow]>;
> 
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=155618&r1=155617&r2=155618&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Apr 26 01:40:15 2012
> @@ -196,8 +196,7 @@
>    if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
>    if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
>    if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
> -  // FIXME: AVX codegen support is not ready.
> -  //if ((ECX >> 28) & 1) { X86SSELevel = AVX;  ToggleFeature(X86::FeatureAVX); }
> +  if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }
>  
>    bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
>    bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
> @@ -299,11 +298,10 @@
>          HasBMI = true;
>          ToggleFeature(X86::FeatureBMI);
>        }
> -      // FIXME: AVX2 codegen support is not ready.
> -      //if ((EBX >> 5) & 0x1) {
> -      //  X86SSELevel = AVX2;
> -      //  ToggleFeature(X86::FeatureAVX2);
> -      //}
> +      if ((EBX >> 5) & 0x1) {
> +        X86SSELevel = AVX2;
> +        ToggleFeature(X86::FeatureAVX2);
> +      }
>        if ((EBX >> 8) & 0x1) {
>          HasBMI2 = true;
>          ToggleFeature(X86::FeatureBMI2);
> 
> 
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