[llvm-commits] [llvm] r155685 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
Jim Grosbach
grosbach at apple.com
Fri Apr 27 09:53:48 PDT 2012
On Apr 27, 2012, at 1:00 AM, James Molloy <James.Molloy at arm.com> wrote:
> Hi Evan,
>
> I'm not certain about this commit;
>
>> def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
>> "isb", "\t$opt",
>> - []>, Requires<[IsThumb2, HasDB]> {
>> + []>, Requires<[IsThumb, HasDB]> {
>
> ISB is definitely a Thumb2 instruction, not a thumb1 instruction. I'm
> therefore uncertain about the changing of the predicate from IsThumb2 to
> IsThumb.
>
Right. That's captured by the HasDB predicate.
> That the M0 supports this is an extension specific to architecture V6M -
> perhaps creating a new predicate (maybe equivalent to IsThumb2 || (IsThumb
> && IsMClass) ) might be a more canonical way of doing it?
>
> You're the code owner though so please feel free to tell me to be quiet :)
>
>
> +def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
> +def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
> +def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
>
> Same here - also you change the t2ISB instruction's predicate and these
> aliases' but not the definition of t2DSB or t2DMB - is this deliberate?
>
> That these instructions work for M0 is not tested in the testcase.
>
> Cheers,
>
> James
>
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu
> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng
> Sent: 27 April 2012 02:27
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [llvm] r155685 - in /llvm/trunk:
> lib/Target/ARM/ARMInstrThumb2.td
> lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
>
> Author: evancheng
> Date: Thu Apr 26 20:27:19 2012
> New Revision: 155685
>
> URL: http://llvm.org/viewvc/llvm-project?rev=155685&view=rev
> Log:
> - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
> instructions.
> - However, it does support dmb, dsb, isb, mrs, and msr.
> rdar://11331541
>
> Added:
> llvm/trunk/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2
> .td?rev=155685&r1=155684&r2=155685&view=diff
> ============================================================================
> ==
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Apr 26 20:27:19 2012
> @@ -3017,7 +3017,7 @@
>
> def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
> "isb", "\t$opt",
> - []>, Requires<[IsThumb2, HasDB]> {
> + []>, Requires<[IsThumb, HasDB]> {
> bits<4> opt;
> let Inst{31-4} = 0xf3bf8f6;
> let Inst{3-0} = opt;
> @@ -3646,7 +3646,7 @@
> // the A/R class (a full msr_mask).
> def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
> "mrs", "\t$Rd, $mask", []>,
> - Requires<[IsThumb2,IsMClass]> {
> + Requires<[IsThumb,IsMClass]> {
> bits<4> Rd;
> bits<8> mask;
> let Inst{31-12} = 0b11110011111011111000;
> @@ -3682,7 +3682,7 @@
> // Move from ARM core register to Special Register
> def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
> NoItinerary, "msr", "\t$SYSm, $Rn", []>,
> - Requires<[IsThumb2,IsMClass]> {
> + Requires<[IsThumb,IsMClass]> {
> bits<8> SYSm;
> bits<4> Rn;
> let Inst{31-21} = 0b11110011100;
> @@ -4002,9 +4002,9 @@
> (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
>
> // Memory barriers
> -def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
> -def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
> -def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
> +def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
> +def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
> +def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
>
> // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
> // width specifier.
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/A
> RMMCTargetDesc.cpp?rev=155685&r1=155684&r2=155685&view=diff
> ============================================================================
> ==
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Apr 26
> 20:27:19 2012
> @@ -51,23 +51,32 @@
> Idx = 6;
> }
>
> + bool NoCPU = CPU == "generic" || CPU.empty();
> std::string ARMArchFeature;
> if (Idx) {
> unsigned SubVer = TT[Idx];
> if (SubVer >= '7' && SubVer <= '9') {
> if (Len >= Idx+2 && TT[Idx+1] == 'm') {
> - // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
> - ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
> + if (NoCPU)
> + // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
> + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
> + else
> + // Use CPU to figure out the exact features.
> + ARMArchFeature = "+v7";
> } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
> - // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
> - // FeatureT2XtPk, FeatureMClass
> - ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
> + if (NoCPU)
> + // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
> + // FeatureT2XtPk, FeatureMClass
> + ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
> + else
> + // Use CPU to figure out the exact features.
> + ARMArchFeature = "+v7";
> } else {
> // v7 CPUs have lots of different feature sets. If no CPU is
> specified,
> // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
> // the "minimum" feature set and use CPU string to figure out the
> exact
> // features.
> - if (CPU == "generic")
> + if (NoCPU)
> // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
> ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
> else
> @@ -77,10 +86,13 @@
> } else if (SubVer == '6') {
> if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
> ARMArchFeature = "+v6t2";
> - else if (Len >= Idx+2 && TT[Idx+1] == 'm')
> - // v6m: FeatureNoARM, FeatureMClass
> - ARMArchFeature = "+v6t2,+noarm,+mclass";
> - else
> + else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
> + if (NoCPU)
> + // v6m: FeatureNoARM, FeatureMClass
> + ARMArchFeature = "+v6,+noarm,+mclass";
> + else
> + ARMArchFeature = "+v6";
> + } else
> ARMArchFeature = "+v6";
> } else if (SubVer == '5') {
> if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
>
> Added: llvm/trunk/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2012-04-26
> -M0ISelBug.ll?rev=155685&view=auto
> ============================================================================
> ==
> --- llvm/trunk/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll (added)
> +++ llvm/trunk/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll Thu Apr 26
> 20:27:19 2012
> @@ -0,0 +1,12 @@
> +; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
> +; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs,
> etc.)
> +; rdar://11331541
> +
> +define i32 @t(i32 %a) nounwind {
> +; CHECK: t:
> +; CHECK: asrs r1, r0, #31
> +; CHECK: eors r1, r0
> + %tmp0 = ashr i32 %a, 31
> + %tmp1 = xor i32 %tmp0, %a
> + ret i32 %tmp1
> +}
>
>
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