[llvm-commits] FW: [PATCH] Implement unallocated NOP Hints

[Richard Barton]

Hello all

Apologies, there was a slight error in the original patch. The attached patch is
correct.

Thanks 
Rich

-----Original Message-----
From: Richard Barton [mailto:richard.barton at arm.com] 
Sent: 25 April 2012 13:34
To: llvm-commits at cs.uiuc.edu
Cc: 'Bill Wendling'; 'Jim Grosbach'
Subject: [PATCH] Implement unallocated NOP Hints 

Hi Bill

They keep coming... another IT patch. I have cc-ed Jim as he has been helping
with these types of code reviews recently.

The attached patch implements unallocated NOP Hints in MC. These are 16-bit
Thumb instructions with encoding:

15     12      8       4       0
|1,0,1,1|1,1,1,1|  opA  |  opB  |

[the below table is from: ARMARM 6.2.5. Miscellaneous 16-bit instructions]

Table 6.7. 16-bit If-Then and hint instructions
opA	opB		Instruction			See	Variant
-	not 0000	If-Then			IT	v6T2
0000	0000		No Operation hint		NOP	v6T2
0001	0000		Yield hint			YIELD	v7
0010	0000		Wait For Event hint	WFE	v7
0011	0000		Wait For Interrupt hint	WFI	v7
0100	0000		Send Event hint		SEV	v7

current MC Behaviour
---------------------
For pre-v6T2:
 - YIELD, SEV, WFI, WFE instructions incorrectly decode to v6T2 versions. 
 - NOP incorrectly decode as undefined instructions.
 - IT was incorrectly decode as undefined instructions. 
 - Any other hints incorrectly decode as undefined instructions.

For v6T2 and later:
 - YIELD, etc. instructions decode (this is correct for v7 but not for v6T2)
 - NOP correctly decode.
 - IT correctly decode.
 - Any other hints incorrectly decode as unpredictable IT instructions.

My patch adds a new tablegen class to match these only for pre-v6T2. These will
disassemble as: 
"nop @ UNALLOCATED opA = #<num> opB = #<num>"

This is mildly unpleasant in that it adds a dependency on the comment character.
It will can also never be assembled, but this is fine as the ARMARM says
"software must not use them." 

I opted for this approach as it allows the opcode fields to be expressed in the
tablegen as Operand types, which means that there is no need for a specialist
decoder and encoder.

Patched MC behaviour
--------------------
For pre-v6T2:
 - All such instructions are decoded as unallocated NOPs, and disassembled as
shown.

For v6T2:
 - NOP and IT behaviour unchanged
 - YIELD, SEV, etc. decoded as predictable, unallocated NOPs and disassembled as
shown.
 - All other instructions decoded as predictable, unallocated NOPs and
disassembled as shown.

For V7 and later:
 - NOP and IT behaviour unchanged
 - YIELD, SEV, etc. behaviour unchanged from old v6T2 and later behaviour
 - All other instructions decoded as predictable, unallocated NOPs and
disassembled as shown.

In order to do this I had to implement the NoV6T2 predicate so that tablegen
could output an if statement in the disassembler to correspond to it.
 
My patch also updates tests that incorrectly disassemble yield, sev, etc for
thumb1.

Please review.

Thanks,
Richard Barton
ARM Ltd, Cambridge

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