[llvm-commits] [llvm] r155453 - in /llvm/trunk/test/MC/Disassembler/ARM: neon.txt neont2.txt

[Kevin Enderby]

Author: enderby
Date: Tue Apr 24 12:45:56 2012
New Revision: 155453

URL: http://llvm.org/viewvc/llvm-project?rev=155453&view=rev
Log:
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/neon.txt
    llvm/trunk/test/MC/Disassembler/ARM/neont2.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon.txt?rev=155453&r1=155452&r2=155453&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon.txt Tue Apr 24 12:45:56 2012
@@ -1734,6 +1734,25 @@
 0xcf 0x1a 0xe0 0xf4
 # CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
 
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]
+0x0f 0x0e 0xa4 0xf4
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]!
+0x0d 0x0e 0xa4 0xf4
+# CHECK: vld3.8	{d0[], d2[], d4[]}, [r4], r5
+0x25 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4]
+0x6f 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d1[], d2[]}, [r4]!
+0x4d 0x0e 0xa4 0xf4
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4], r5
+0x65 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]
+0x8f 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]!
+0x8d 0x0e 0xa4 0xf4
+# CHECK: vld3.32	{d0[], d2[], d4[]}, [r4], r5
+0xa5 0x0e 0xa4 0xf4
+
 0x3f 0x03 0xe0 0xf4
 # CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
 0x4f 0x07 0xe0 0xf4

Modified: llvm/trunk/test/MC/Disassembler/ARM/neont2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neont2.txt?rev=155453&r1=155452&r2=155453&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neont2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neont2.txt Tue Apr 24 12:45:56 2012
@@ -1475,6 +1475,25 @@
 0xe0 0xf9 0xcf 0x1a
 # CHECK: vld3.32	{d17[1], d19[1], d21[1]}, [r0]
 
+0xa4 0xf9 0x0f 0x0e
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]
+0xa4 0xf9 0x0d 0x0e
+# CHECK: vld3.8	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0x25 0x0e
+# CHECK: vld3.8	{d0[], d2[], d4[]}, [r4], r5
+0xa4 0xf9 0x6f 0x0e
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4]
+0xa4 0xf9 0x4d 0x0e
+# CHECK: vld3.16	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0x65 0x0e
+# CHECK: vld3.16	{d0[], d2[], d4[]}, [r4], r5
+0xa4 0xf9 0x8f 0x0e
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]
+0xa4 0xf9 0x8d 0x0e
+# CHECK: vld3.32	{d0[], d1[], d2[]}, [r4]!
+0xa4 0xf9 0xa5 0x0e
+# CHECK: vld3.32	{d0[], d2[], d4[]}, [r4], r5
+
 0xe0 0xf9 0x3f 0x03
 # CHECK: vld4.8	{d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
 0xe0 0xf9 0x4f 0x07