[llvm-commits] [llvm] r155364 - in /llvm/trunk: include/llvm/CodeGen/DFAPacketizer.h lib/CodeGen/DFAPacketizer.cpp
Tom Stellard
thomas.stellard at amd.com
Mon Apr 23 11:27:52 PDT 2012
Hi Sirish,
Thanks for splitting this off into a separate patch.
I'm still running into the same assertion assertion failure I was
before:
ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels!
I can get around this now by setting
DeafaultVLIWScheduler::CanHandleTerminators = true;
So, it might be useful to expose this to the interface somehow, though
I'm not sure if this is the correct solution.
Otherwise it looks good.
-Tom
On Mon, Apr 23, 2012 at 05:49:10PM +0000, Sirish Pande wrote:
> Author: sirish
> Date: Mon Apr 23 12:49:09 2012
> New Revision: 155364
>
> URL: http://llvm.org/viewvc/llvm-project?rev=155364&view=rev
> Log:
> Hexagon Packetizer's target independent fix.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
> llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=155364&r1=155363&r2=155364&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Mon Apr 23 12:49:09 2012
> @@ -28,6 +28,7 @@
>
> #include "llvm/CodeGen/MachineBasicBlock.h"
> #include "llvm/ADT/DenseMap.h"
> +#include <map>
>
> namespace llvm {
>
> @@ -36,7 +37,7 @@
> class MachineLoopInfo;
> class MachineDominatorTree;
> class InstrItineraryData;
> -class ScheduleDAGInstrs;
> +class DefaultVLIWScheduler;
> class SUnit;
>
> class DFAPacketizer {
> @@ -77,6 +78,8 @@
> // reserveResources - Reserve the resources occupied by a machine
> // instruction and change the current state to reflect that change.
> void reserveResources(llvm::MachineInstr *MI);
> +
> + const InstrItineraryData *getInstrItins() const { return InstrItins; }
> };
>
> // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
> @@ -87,20 +90,21 @@
> // and machine resource is marked as taken. If any dependency is found, a target
> // API call is made to prune the dependence.
> class VLIWPacketizerList {
> +protected:
> const TargetMachine &TM;
> const MachineFunction &MF;
> const TargetInstrInfo *TII;
>
> - // Encapsulate data types not exposed to the target interface.
> - ScheduleDAGInstrs *SchedulerImpl;
> + // The VLIW Scheduler.
> + DefaultVLIWScheduler *VLIWScheduler;
>
> -protected:
> // Vector of instructions assigned to the current packet.
> std::vector<MachineInstr*> CurrentPacketMIs;
> // DFA resource tracker.
> DFAPacketizer *ResourceTracker;
> - // Scheduling units.
> - std::vector<SUnit> SUnits;
> +
> + // Generate MI -> SU map.
> + std::map<MachineInstr*, SUnit*> MIToSUnit;
>
> public:
> VLIWPacketizerList(
> @@ -118,17 +122,32 @@
> DFAPacketizer *getResourceTracker() {return ResourceTracker;}
>
> // addToPacket - Add MI to the current packet.
> - void addToPacket(MachineInstr *MI);
> + virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
> + MachineBasicBlock::iterator MII = MI;
> + CurrentPacketMIs.push_back(MI);
> + ResourceTracker->reserveResources(MI);
> + return MII;
> + }
>
> // endPacket - End the current packet.
> - void endPacket(MachineBasicBlock *MBB, MachineInstr *I);
> + void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
> +
> + // initPacketizerState - perform initialization before packetizing
> + // an instruction. This function is supposed to be overrided by
> + // the target dependent packetizer.
> + virtual void initPacketizerState(void) { return; }
>
> // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
> - bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB);
> + virtual bool ignorePseudoInstruction(MachineInstr *I,
> + MachineBasicBlock *MBB) {
> + return false;
> + }
>
> - // isSoloInstruction - return true if instruction I must end previous
> - // packet.
> - bool isSoloInstruction(MachineInstr *I);
> + // isSoloInstruction - return true if instruction MI can not be packetized
> + // with any other instruction, which means that MI itself is a packet.
> + virtual bool isSoloInstruction(MachineInstr *MI) {
> + return true;
> + }
>
> // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
> // together.
> @@ -141,6 +160,7 @@
> virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
> return false;
> }
> +
> };
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=155364&r1=155363&r2=155364&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)
> +++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Mon Apr 23 12:49:09 2012
> @@ -23,10 +23,10 @@
> //
> //===----------------------------------------------------------------------===//
>
> +#include "llvm/CodeGen/ScheduleDAGInstrs.h"
> #include "llvm/CodeGen/DFAPacketizer.h"
> #include "llvm/CodeGen/MachineInstr.h"
> #include "llvm/CodeGen/MachineInstrBundle.h"
> -#include "llvm/CodeGen/ScheduleDAGInstrs.h"
> #include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/MC/MCInstrItineraries.h"
> using namespace llvm;
> @@ -100,22 +100,23 @@
> reserveResources(&MID);
> }
>
> -namespace {
> +namespace llvm {
> // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
> // Schedule method to build the dependence graph.
> class DefaultVLIWScheduler : public ScheduleDAGInstrs {
> public:
> DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
> - MachineDominatorTree &MDT, bool IsPostRA);
> + MachineDominatorTree &MDT, bool IsPostRA);
> // Schedule - Actual scheduling work.
> void schedule();
> };
> -} // end anonymous namespace
> +}
>
> DefaultVLIWScheduler::DefaultVLIWScheduler(
> MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
> bool IsPostRA) :
> ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
> + CanHandleTerminators = true;
> }
>
> void DefaultVLIWScheduler::schedule() {
> @@ -129,49 +130,25 @@
> bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
> TII = TM.getInstrInfo();
> ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
> - SchedulerImpl = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
> + VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
> }
>
> // VLIWPacketizerList Dtor
> VLIWPacketizerList::~VLIWPacketizerList() {
> - delete SchedulerImpl;
> - delete ResourceTracker;
> -}
> -
> -// ignorePseudoInstruction - ignore pseudo instructions.
> -bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
> - MachineBasicBlock *MBB) {
> - if (MI->isDebugValue())
> - return true;
> -
> - if (TII->isSchedulingBoundary(MI, MBB, MF))
> - return true;
> -
> - return false;
> -}
> -
> -// isSoloInstruction - return true if instruction I must end previous
> -// packet.
> -bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) {
> - if (I->isInlineAsm())
> - return true;
> -
> - return false;
> -}
> + if (VLIWScheduler)
> + delete VLIWScheduler;
>
> -// addToPacket - Add I to the current packet and reserve resource.
> -void VLIWPacketizerList::addToPacket(MachineInstr *MI) {
> - CurrentPacketMIs.push_back(MI);
> - ResourceTracker->reserveResources(MI);
> + if (ResourceTracker)
> + delete ResourceTracker;
> }
>
> // endPacket - End the current packet, bundle packet instructions and reset
> // DFA state.
> void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
> - MachineInstr *I) {
> + MachineInstr *MI) {
> if (CurrentPacketMIs.size() > 1) {
> MachineInstr *MIFirst = CurrentPacketMIs.front();
> - finalizeBundle(*MBB, MIFirst, I);
> + finalizeBundle(*MBB, MIFirst, MI);
> }
> CurrentPacketMIs.clear();
> ResourceTracker->clearResources();
> @@ -181,31 +158,37 @@
> void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
> MachineBasicBlock::iterator BeginItr,
> MachineBasicBlock::iterator EndItr) {
> - assert(MBB->end() == EndItr && "Bad EndIndex");
> -
> - SchedulerImpl->enterRegion(MBB, BeginItr, EndItr, MBB->size());
> -
> - // Build the DAG without reordering instructions.
> - SchedulerImpl->schedule();
> -
> - // Remember scheduling units.
> - SUnits = SchedulerImpl->SUnits;
> + assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
> + VLIWScheduler->startBlock(MBB);
> + VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
> + VLIWScheduler->schedule();
> + VLIWScheduler->exitRegion();
> +
> + // Generate MI -> SU map.
> + //std::map <MachineInstr*, SUnit*> MIToSUnit;
> + MIToSUnit.clear();
> + for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
> + SUnit *SU = &VLIWScheduler->SUnits[i];
> + MIToSUnit[SU->getInstr()] = SU;
> + }
>
> // The main packetizer loop.
> for (; BeginItr != EndItr; ++BeginItr) {
> MachineInstr *MI = BeginItr;
>
> - // Ignore pseudo instructions.
> - if (ignorePseudoInstruction(MI, MBB))
> - continue;
> + this->initPacketizerState();
>
> // End the current packet if needed.
> - if (isSoloInstruction(MI)) {
> + if (this->isSoloInstruction(MI)) {
> endPacket(MBB, MI);
> continue;
> }
>
> - SUnit *SUI = SchedulerImpl->getSUnit(MI);
> + // Ignore pseudo instructions.
> + if (this->ignorePseudoInstruction(MI, MBB))
> + continue;
> +
> + SUnit *SUI = MIToSUnit[MI];
> assert(SUI && "Missing SUnit Info!");
>
> // Ask DFA if machine resource is available for MI.
> @@ -215,13 +198,13 @@
> for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
> VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
> MachineInstr *MJ = *VI;
> - SUnit *SUJ = SchedulerImpl->getSUnit(MJ);
> + SUnit *SUJ = MIToSUnit[MJ];
> assert(SUJ && "Missing SUnit Info!");
>
> // Is it legal to packetize SUI and SUJ together.
> - if (!isLegalToPacketizeTogether(SUI, SUJ)) {
> + if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
> // Allow packetization if dependency can be pruned.
> - if (!isLegalToPruneDependencies(SUI, SUJ)) {
> + if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
> // End the packet if dependency cannot be pruned.
> endPacket(MBB, MI);
> break;
> @@ -234,11 +217,9 @@
> }
>
> // Add MI to the current packet.
> - addToPacket(MI);
> + BeginItr = this->addToPacket(MI);
> } // For all instructions in BB.
>
> // End any packet left behind.
> endPacket(MBB, EndItr);
> -
> - SchedulerImpl->exitRegion();
> }
>
>
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