[llvm-commits] Review Request: test case for: r154955

[Evan Cheng]

Some nitpicks:

1. No need for ModuleID, target data, etc. They can usually be stripped.
2. Rather than leaving the target triple in, just specify it as  command line option -mtriple=...
3. Put radar number after run like this: ; rdar://11195364

In the future, as long as you follow the right convention, test cases do not need to be reviewed before commit.

Evan

On Apr 19, 2012, at 11:35 AM, Joel Jones wrote:

> Test for the the problem with xors being changed into ands
> when the set bits aren't the same for both args of the xor.
> This transformation is in the function TargetLowering::SimplifyDemandedBits
> in the file lib/CodeGen/SelectionDAG/TargetLowering.cpp.
> 
> I have tested this test using a previous version of llc which the defect and the
> a version of llc which does not. I got the expected fail and pass, respectively.
> 
> Joel Jones
> 
> Index: test/CodeGen/X86/targetLoweringGeneric.ll
> ===================================================================
> --- test/CodeGen/X86/targetLoweringGeneric.ll	(revision 0)
> +++ test/CodeGen/X86/targetLoweringGeneric.ll	(revision 0)
> @@ -0,0 +1,42 @@
> +; RUN: llc -fast-isel=false -O0 < %s | FileCheck %s
> +
> +; Gather non-machine specific tests for the transformations in
> +; CodeGen/SelectionDAG/TargetLowering.  Currently, these
> +; can't be tested easily by checking the SDNodes that are
> +; the data structures that these transformations act on.
> +; Therefore, use X86 assembler output to check against.
> +
> +; ModuleID = 'startToOptOptBad.bc'
> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-f128:128:128-n8:16:32"
> +target triple = "i386-apple-darwin9"
> +
> +; Radar: 11195364 A problem with the transformation:
> +;  If all of the demanded bits on one side are known, and all of the set
> +;  bits on that side are also known to be set on the other side, turn this
> +;  into an AND, as we know the bits will be cleared.
> +; The known set (one) bits for the arguments %xor1 are not the same, so the
> +; transformation should not occur
> +define void @foo(i32 %i32In1, i32 %i32In2, i32 %i32In3, i32 %i32In4, 
> +                 i32 %i32In5, i32 %i32In6, i32* %i32StarOut, i1 %i1In1, 
> +                 i32* %i32SelOut) nounwind {
> +    %and3 = and i32 %i32In1, 1362779777
> +    %or2 = or i32 %i32In2, %i32In3
> +    %and2 = and i32 %or2, 1362779777
> +    %xor3 = xor i32 %and3, %and2
> +    ; CHECK: shll
> +    %shl1 = shl i32 %xor3, %i32In4
> +    %sub1 = sub i32 %or2, %shl1
> +    %add1 = add i32 %sub1, %i32In5
> +    %and1 = and i32 %add1, 1
> +    %xor2 = xor i32 %and1, 1
> +    %or1 = or i32 %xor2, 364806994 ;0x15BE8352
> +    ; CHECK-NOT: andl $96239955
> +    %xor1 = xor i32 %or1, 268567040 ;0x10020200
> +    ; force an output so not DCE'd
> +    store i32 %xor1, i32* %i32StarOut
> +    ; force not fast isel by using a select
> +    %i32SelVal = select i1 %i1In1, i32 %i32In1, i32 %xor1
> +    store i32 %i32SelVal, i32* %i32SelOut
> +    ; CHECK: ret
> +    ret void
> +}
> 
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