[llvm-commits] [llvm] r155004 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/unpredictable-swp-arm.txt

[Silviu Baranga]

Author: sbaranga
Date: Wed Apr 18 09:18:57 2012
New Revision: 155004

URL: http://llvm.org/viewvc/llvm-project?rev=155004&view=rev
Log:
Added support for disassembling unpredictable swp/swpb ARM instructions.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=155004&r1=155003&r2=155004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Apr 18 09:18:57 2012
@@ -532,6 +532,7 @@
   let Inst{11-4} = 0b00001001;
   let Inst{3-0} = Rt2;
 
+  let Unpredictable{11-8} = 0b1111;
   let DecoderMethod = "DecodeSwap";
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=155004&r1=155003&r2=155004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 18 09:18:57 2012
@@ -4280,9 +4280,9 @@
 
 // SWP/SWPB are deprecated in V6/V7.
 let mayLoad = 1, mayStore = 1 in {
-def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
+def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
                 "swp", []>;
-def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
+def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
                 "swpb", []>;
 }
 

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=155004&r1=155003&r2=155004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Apr 18 09:18:57 2012
@@ -4310,6 +4310,10 @@
     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
   DecodeStatus S = MCDisassembler::Success;
+
+  if (Rt == Rn || Rn == Rt2)
+    S = MCDisassembler::SoftFail;
+
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))

Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt?rev=155004&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt Wed Apr 18 09:18:57 2012
@@ -0,0 +1,26 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x9f 0x10 0x03 0x01
+0x9f 0x10 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0xf0 0x03 0x01
+0x90 0xf0 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x1f 0x03 0x01
+0x90 0x1f 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x0f 0x01
+0x90 0x10 0x0f 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x01 0x01
+0x90 0x10 0x01 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x00 0x01
+0x90 0x10 0x00 0x01
+