[llvm-commits] [llvm] r154999 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt

[Silviu Baranga]

Author: sbaranga
Date: Wed Apr 18 07:48:43 2012
New Revision: 154999

URL: http://llvm.org/viewvc/llvm-project?rev=154999&view=rev
Log:
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=154999&r1=154998&r2=154999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 18 07:48:43 2012
@@ -1187,6 +1187,8 @@
     let Inst{19-16} = Rn;
     let Inst{15-12} = 0b0000;
     let Inst{11-0} = imm;
+
+    let Unpredictable{15-12} = 0b1111;
   }
   def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
                opc, "\t$Rn, $Rm",
@@ -1200,6 +1202,8 @@
     let Inst{15-12} = 0b0000;
     let Inst{11-4} = 0b00000000;
     let Inst{3-0} = Rm;
+
+    let Unpredictable{15-12} = 0b1111;
   }
   def rsi : AI1<opcod, (outs),
                (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
@@ -1214,11 +1218,13 @@
     let Inst{11-5} = shift{11-5};
     let Inst{4} = 0;
     let Inst{3-0} = shift{3-0};
+
+    let Unpredictable{15-12} = 0b1111;
   }
   def rsr : AI1<opcod, (outs),
-               (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
+               (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
                opc, "\t$Rn, $shift",
-               [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
+               [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
     bits<4> Rn;
     bits<12> shift;
     let Inst{25} = 0;
@@ -1230,6 +1236,8 @@
     let Inst{6-5} = shift{6-5};
     let Inst{4} = 1;
     let Inst{3-0} = shift{3-0};
+
+    let Unpredictable{15-12} = 0b1111;
   }
 
 }

Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt?rev=154999&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt Wed Apr 18 07:48:43 2012
@@ -0,0 +1,30 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x01 0x10 0x50 0x03
+0x01 0x10 0x50 0x03
+
+# CHECK: potentially undefined
+# CHECK: 0x82 0x10  0x50 0x01
+0x82 0x10 0x50 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x02 0x10 0x50 0x01
+0x02 0x10 0x50 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x1f 0x01 0x52 0x01
+0x1f 0x01 0x52 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x11 0x52 0x01
+0x10 0x11 0x52 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x0f 0x51 0x01
+0x10 0x0f 0x51 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x01 0x5f 0x01
+0x10 0x01 0x5f 0x01
+