[llvm-commits] [patch] Patches for some unpredictable instructions on ARM
Owen Anderson
resistor at mac.com
Tue Apr 17 10:21:19 PDT 2012
These looks fine to be, but please clean up trailing whitespace before committing.
--Owen
On Apr 17, 2012, at 9:12 AM, Silviu Baranga <silbar01 at arm.com> wrote:
> Hi,
>
> Here are some patches that address the decoding of some unpredictable instructions
> on the ARM backend. All patches add regression tests.
>
> swp.diff - The swp/swpb instructions have some corner cases in which they have
> unpredictable behaviour. The patch adds checks for these cases and
> regression tests.
> AI1_cmp.diff - Sets the unpredictable field for all the cmp, tst, teq, cmnz instructions and adds
> the unpredictability condition for the register-shifted register form when any of the
> register operands are the pc register.
> cdp2.diff - The CDP2 instruction has no restriction on the coprocessor number parameter,
> but in the current implementation the instruction is undefined if the value of the
> coprocessor number is in {1010, 1011}. To fix this we add a new operand type for the coprocessor
> number, which doesn't have that restriction. We replace the coprocessor operand type in
> the CDP2 instruction with the new operand.
> mrrc.diff - The MCRR2/MRRC2 instructions are unpredictable when the coprocessor is in 101X or
> Rt==Rt2 or Rt==15 or Rt2==15. The patch adds C++ code to handle these cases and a
> regression test.
> mrs.diff - The patch adds the soft fail behavior when disassembling MRS instructions. There
> appears to be a collision between the space of unpredictable MRS instructions and
> the space of predictable CPS instructions. The workaround for this was to not set the
> 16th bit in the unpredictability mask of the MRS instruction.
>
>
> Please review these patches.
>
> Thanks,
> Silviu
> <swp.diff><AI1_cmp.diff><cdp2.diff><mrrc.diff><mrs.diff>_______________________________________________
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