[llvm-commits] [llvm] r154840 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-shift-encoding.s
Jim Grosbach
grosbach at apple.com
Mon Apr 16 11:03:17 PDT 2012
Author: grosbach
Date: Mon Apr 16 13:03:16 2012
New Revision: 154840
URL: http://llvm.org/viewvc/llvm-project?rev=154840&view=rev
Log:
ARM assembly two-operand forms for VRSHL.
rdar://11252521
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/test/MC/ARM/neon-shift-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=154840&r1=154839&r2=154840&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Apr 16 13:03:16 2012
@@ -5951,7 +5951,7 @@
def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
(VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
-// VSHL (immediate) two-operand aliases.
+// VSHR (immediate) two-operand aliases.
def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
(VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
@@ -5988,6 +5988,41 @@
def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
(VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
+// VRSHL two-operand aliases.
+def : NEONInstAlias<"vrshl${p}.s8 $Vdn, $Vm",
+ (VRSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s16 $Vdn, $Vm",
+ (VRSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s32 $Vdn, $Vm",
+ (VRSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s64 $Vdn, $Vm",
+ (VRSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u8 $Vdn, $Vm",
+ (VRSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u16 $Vdn, $Vm",
+ (VRSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u32 $Vdn, $Vm",
+ (VRSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u64 $Vdn, $Vm",
+ (VRSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
+
+def : NEONInstAlias<"vrshl${p}.s8 $Vdn, $Vm",
+ (VRSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s16 $Vdn, $Vm",
+ (VRSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s32 $Vdn, $Vm",
+ (VRSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.s64 $Vdn, $Vm",
+ (VRSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u8 $Vdn, $Vm",
+ (VRSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u16 $Vdn, $Vm",
+ (VRSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u32 $Vdn, $Vm",
+ (VRSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+def : NEONInstAlias<"vrshl${p}.u64 $Vdn, $Vm",
+ (VRSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
+
// VLD1 single-lane pseudo-instructions. These need special handling for
// the lane index that an InstAlias can't handle, so we use these instead.
def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=154840&r1=154839&r2=154840&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Mon Apr 16 13:03:16 2012
@@ -429,6 +429,41 @@
@ CHECK: vshl.i32 d4, d4, #17 @ encoding: [0x14,0x45,0xb1,0xf2]
@ CHECK: vshl.i64 d4, d4, #43 @ encoding: [0x94,0x45,0xab,0xf2]
+ @ Two-operand VRSHL forms.
+ vrshl.s8 d11, d4
+ vrshl.s16 d12, d5
+ vrshl.s32 d13, d6
+ vrshl.s64 d14, d7
+ vrshl.u8 d15, d8
+ vrshl.u16 d16, d9
+ vrshl.u32 d17, d10
+ vrshl.u64 d18, d11
+ vrshl.s8 q1, q8
+ vrshl.s16 q2, q15
+ vrshl.s32 q3, q14
+ vrshl.s64 q4, q13
+ vrshl.u8 q5, q12
+ vrshl.u16 q6, q11
+ vrshl.u32 q7, q10
+ vrshl.u64 q8, q9
+
+@ CHECK: vrshl.s8 d11, d11, d4 @ encoding: [0x0b,0xb5,0x04,0xf2]
+@ CHECK: vrshl.s16 d12, d12, d5 @ encoding: [0x0c,0xc5,0x15,0xf2]
+@ CHECK: vrshl.s32 d13, d13, d6 @ encoding: [0x0d,0xd5,0x26,0xf2]
+@ CHECK: vrshl.s64 d14, d14, d7 @ encoding: [0x0e,0xe5,0x37,0xf2]
+@ CHECK: vrshl.u8 d15, d15, d8 @ encoding: [0x0f,0xf5,0x08,0xf3]
+@ CHECK: vrshl.u16 d16, d16, d9 @ encoding: [0x20,0x05,0x59,0xf3]
+@ CHECK: vrshl.u32 d17, d17, d10 @ encoding: [0x21,0x15,0x6a,0xf3]
+@ CHECK: vrshl.u64 d18, d18, d11 @ encoding: [0x22,0x25,0x7b,0xf3]
+@ CHECK: vrshl.s8 q1, q1, q8 @ encoding: [0xc2,0x25,0x00,0xf2]
+@ CHECK: vrshl.s16 q2, q2, q15 @ encoding: [0xc4,0x45,0x1e,0xf2]
+@ CHECK: vrshl.s32 q3, q3, q14 @ encoding: [0xc6,0x65,0x2c,0xf2]
+@ CHECK: vrshl.s64 q4, q4, q13 @ encoding: [0xc8,0x85,0x3a,0xf2]
+@ CHECK: vrshl.u8 q5, q5, q12 @ encoding: [0xca,0xa5,0x08,0xf3]
+@ CHECK: vrshl.u16 q6, q6, q11 @ encoding: [0xcc,0xc5,0x16,0xf3]
+@ CHECK: vrshl.u32 q7, q7, q10 @ encoding: [0xce,0xe5,0x24,0xf3]
+@ CHECK: vrshl.u64 q8, q8, q9 @ encoding: [0xe0,0x05,0x72,0xf3]
+
@ Two-operand forms.
vshr.s8 d15, #8
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