[llvm-commits] [PATCH 02/11] (patch) Mips inline asm: Allow 64 bit integer values in gpu registers if arch and abi are 64 bit

[Jack Carter]

---
 lib/Target/Mips/MipsISelLowering.cpp           |    6 ++++--
 test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll |   21 +++++++++++++++++++++
 test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll   |   20 ++++++++++++++++++++
 3 files changed, 45 insertions(+), 2 deletions(-)
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll
 create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 4d992d3..945ac9c 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2943,8 +2943,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
     case 'r':
       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
         return std::make_pair(0U, Mips::CPURegsRegisterClass);
-      assert(VT == MVT::i64 && "Unexpected type.");
-      return std::make_pair(0U, Mips::CPU64RegsRegisterClass);
+      if (VT == MVT::i64 && HasMips64)
+        return std::make_pair(0U, Mips::CPU64RegsRegisterClass);
+      // This will generate an error message
+      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
     case 'f':
       if (VT == MVT::f32)
         return std::make_pair(0U, Mips::FGR32RegisterClass);
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll
new file mode 100644
index 0000000..df8796a
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.ll
@@ -0,0 +1,21 @@
+;XFAIL:
+;
+; Register constraint "r" shouldn't take long long unless
+; The target is 64 bit.
+;
+;
+; RUN: not llc -march=mipsel < %s 
+
+
+define i32 @main() nounwind {
+entry:
+
+
+; r with long long
+;CHECK:	#APP
+;CHECK:	addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK:	#NO_APP
+  tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
+  ret i32 0
+}
+
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
new file mode 100644
index 0000000..7870666
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
@@ -0,0 +1,20 @@
+;
+; Register constraint "r" shouldn't take long long unless
+; The target is 64 bit.
+;
+;
+; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
+
+
+define i32 @main() nounwind {
+entry:
+
+
+; r with long long
+;CHECK:	#APP
+;CHECK:	addi ${{[0-9]+}},${{[0-9]+}},3
+;CHECK:	#NO_APP
+  tail call i64 asm sideeffect "addi $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind
+  ret i32 0
+}
+