[llvm-commits] [llvm] r154518 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h utils/TableGen/CodeGenRegisters.cpp utils/TableGen/CodeGenRegisters.h utils/TableGen/RegisterInfoEmitter.cpp
Andrew Trick
atrick at apple.com
Wed Apr 11 11:16:28 PDT 2012
Author: atrick
Date: Wed Apr 11 13:16:28 2012
New Revision: 154518
URL: http://llvm.org/viewvc/llvm-project?rev=154518&view=rev
Log:
TableGen's regpressure: emit per-registerclass weight limits.
Modified:
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
llvm/trunk/utils/TableGen/CodeGenRegisters.h
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=154518&r1=154517&r2=154518&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Apr 11 13:16:28 2012
@@ -202,6 +202,13 @@
bool inAllocatableClass; // Register belongs to an allocatable regclass.
};
+/// Each TargetRegisterClass has a per register weight, and weight
+/// limit which must be less than the limits of its pressure sets.
+struct RegClassWeight {
+ unsigned RegWeigt;
+ unsigned WeightLimit;
+};
+
/// TargetRegisterInfo base class - We assume that the target defines a static
/// array of TargetRegisterDesc objects that represent all of the machine
/// registers that the target has. As such, we simply have to track a pointer
@@ -509,7 +516,8 @@
}
/// Get the weight in units of pressure for this register class.
- virtual unsigned getRegClassWeight(const TargetRegisterClass *RC) const = 0;
+ virtual const RegClassWeight &getRegClassWeight(
+ const TargetRegisterClass *RC) const = 0;
/// Get the number of dimensions of register pressure.
virtual unsigned getNumRegPressureSets() const = 0;
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=154518&r1=154517&r2=154518&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Wed Apr 11 13:16:28 2012
@@ -722,6 +722,16 @@
Out.set((*I)->EnumValue);
}
+// Populate a unique sorted list of units from a register set.
+void CodeGenRegisterClass::buildRegUnitSet(
+ std::vector<unsigned> &RegUnits) const {
+ std::vector<unsigned> TmpUnits;
+ for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI)
+ TmpUnits.push_back(*UnitI);
+ std::sort(TmpUnits.begin(), TmpUnits.end());
+ std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
+ std::back_inserter(RegUnits));
+}
//===----------------------------------------------------------------------===//
// CodeGenRegBank
@@ -1130,17 +1140,6 @@
}
}
-// Populate a unique sorted list of units from a register set.
-static void buildRegUnitSet(const CodeGenRegister::Set &Regs,
- std::vector<unsigned> &RegUnits) {
- std::vector<unsigned> TmpUnits;
- for (RegUnitIterator UnitI(Regs); UnitI.isValid(); ++UnitI)
- TmpUnits.push_back(*UnitI);
- std::sort(TmpUnits.begin(), TmpUnits.end());
- std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
- std::back_inserter(RegUnits));
-}
-
// Find a set in UniqueSets with the same elements as Set.
// Return an iterator into UniqueSets.
static std::vector<RegUnitSet>::const_iterator
@@ -1216,7 +1215,7 @@
RegUnitSets.back().Name = RegClasses[RCIdx]->getName();
// Compute a sorted list of units in this class.
- buildRegUnitSet(RegClasses[RCIdx]->getMembers(), RegUnitSets.back().Units);
+ RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units);
// Find an existing RegUnitSet.
std::vector<RegUnitSet>::const_iterator SetI =
@@ -1279,7 +1278,7 @@
// Recompute the sorted list of units in this class.
std::vector<unsigned> RegUnits;
- buildRegUnitSet(RegClasses[RCIdx]->getMembers(), RegUnits);
+ RegClasses[RCIdx]->buildRegUnitSet(RegUnits);
// Don't increase pressure for unallocatable regclasses.
if (RegUnits.empty())
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=154518&r1=154517&r2=154518&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Wed Apr 11 13:16:28 2012
@@ -279,6 +279,9 @@
// getOrder(0).
const CodeGenRegister::Set &getMembers() const { return Members; }
+ // Populate a unique sorted list of units from a register set.
+ void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
+
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
// A key representing the parts of a register class used for forming
@@ -449,6 +452,15 @@
return RegUnitWeights[RUID];
}
+ // Get the sum of unit weights.
+ unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
+ unsigned Weight = 0;
+ for (std::vector<unsigned>::const_iterator
+ I = Units.begin(), E = Units.end(); I != E; ++I)
+ Weight += getRegUnitWeight(*I);
+ return Weight;
+ }
+
// Increase a RegUnitWeight.
void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
RegUnitWeights[RUID] += Inc;
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=154518&r1=154517&r2=154518&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Apr 11 13:16:28 2012
@@ -125,19 +125,23 @@
unsigned NumSets = RegBank.getNumRegPressureSets();
OS << "/// Get the weight in units of pressure for this register class.\n"
- << "unsigned " << ClassName << "::\n"
+ << "const RegClassWeight &" << ClassName << "::\n"
<< "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
- << " static const unsigned RCWeightTable[] = {\n";
+ << " static const RegClassWeight RCWeightTable[] = {\n";
for (unsigned i = 0, e = NumRCs; i != e; ++i) {
const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
const CodeGenRegister::Set &Regs = RC.getMembers();
if (Regs.empty())
- OS << " 0";
- else
- OS << " " << (*Regs.begin())->getWeight(RegBank);
- OS << ", \t// " << RC.getName() << "\n";
+ OS << " {0, 0";
+ else {
+ std::vector<unsigned> RegUnits;
+ RC.buildRegUnitSet(RegUnits);
+ OS << " {" << (*Regs.begin())->getWeight(RegBank)
+ << ", " << RegBank.getRegUnitSetWeight(RegUnits);
+ }
+ OS << "}, \t// " << RC.getName() << "\n";
}
- OS << " 0 };\n"
+ OS << " {0, 0} };\n"
<< " return RCWeightTable[RC->getID()];\n"
<< "}\n\n";
@@ -153,12 +157,7 @@
<< " static const unsigned PressureLimitTable[] = {\n";
for (unsigned i = 0; i < NumSets; ++i ) {
const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
- unsigned Weight = 0;
- for (RegUnitSet::iterator
- I = RegUnits.Units.begin(), E = RegUnits.Units.end(); I != E; ++I) {
- Weight += RegBank.getRegUnitWeight(*I);
- }
- OS << " " << Weight
+ OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
<< ", \t// " << i << ": " << RegBank.getRegPressureSet(i).Name << "\n";
}
OS << " 0 };\n"
@@ -668,7 +667,8 @@
<< " const TargetRegisterClass *getMatchingSuperRegClass("
"const TargetRegisterClass*, const TargetRegisterClass*, "
"unsigned) const;\n"
- << " unsigned getRegClassWeight(const TargetRegisterClass *RC) const;\n"
+ << " const RegClassWeight &getRegClassWeight("
+ << "const TargetRegisterClass *RC) const;\n"
<< " unsigned getNumRegPressureSets() const;\n"
<< " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
<< " const int *getRegClassPressureSets("
More information about the llvm-commits
mailing list