[llvm-commits] [llvm] r154397 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Owen Anderson]

Nadav,

This is causing CodeGen/X86/vec_shuffle-20.ll to fail on Darwin.  I'm going to revert it to unblock the buildbots.

--Owen

On Apr 10, 2012, at 7:58 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:

> Author: nadav
> Date: Tue Apr 10 09:58:31 2012
> New Revision: 154397
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=154397&view=rev
> Log:
> Fix a dagcombine optimization which assumes that the vsetcc result type is always
> of the same size as the compared values. This is ture for SSE/AVX/NEON but not
> for all targets.
> 
> 
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=154397&r1=154396&r2=154397&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 10 09:58:31 2012
> @@ -4354,12 +4354,17 @@
>     // Only do this before legalize for now.
>     if (VT.isVector() && !LegalOperations) {
>       EVT N0VT = N0.getOperand(0).getValueType();
> +      // On some architectures (such as SSE/NEON/etc)the SETCC result type is
> +      // of the same size as the compared operands. Only optimize sext(setcc())
> +      // if this is the case.
> +      EVT SVT = TLI.getSetCCResultType(N0VT);
> +
>         // We know that the # elements of the results is the same as the
>         // # elements of the compare (and the # elements of the compare result
>         // for that matter).  Check to see that they are the same size.  If so,
>         // we know that the element size of the sext'd result matches the
>         // element size of the compare operands.
> -      if (VT.getSizeInBits() == N0VT.getSizeInBits())
> +      if (VT.getSizeInBits() == SVT.getSizeInBits())
>         return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
>                              N0.getOperand(1),
>                              cast<CondCodeSDNode>(N0.getOperand(2))->get());
> @@ -4373,11 +4378,13 @@
>         EVT MatchingVectorType =
>           EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
>                            N0VT.getVectorNumElements());
> -        SDValue VsetCC =
> -          DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
> -                        N0.getOperand(1),
> -                        cast<CondCodeSDNode>(N0.getOperand(2))->get());
> -        return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
> +
> +        if (SVT == MatchingVectorType) {
> +          SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
> +                                 N0.getOperand(0), N0.getOperand(1),
> +                                 cast<CondCodeSDNode>(N0.getOperand(2))->get());
> +          return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
> +        }
>       }
>     }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits