[llvm-commits] [llvm] r154033 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/README.txt test/CodeGen/ARM/commute-movcc.ll test/CodeGen/ARM/machine-cse-cmp.ll test/CodeGen/ARM/select-imm.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Wed Apr 4 11:23:43 PDT 2012
Author: stoklund
Date: Wed Apr 4 13:23:42 2012
New Revision: 154033
URL: http://llvm.org/viewvc/llvm-project?rev=154033&view=rev
Log:
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.
<rdar://problem/11182914>
Added:
llvm/trunk/test/CodeGen/ARM/commute-movcc.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/README.txt
llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
llvm/trunk/test/CodeGen/ARM/select-imm.ll
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Apr 4 13:23:42 2012
@@ -1500,6 +1500,29 @@
llvm_unreachable("Unknown unconditional branch opcode!");
}
+/// commuteInstruction - Handle commutable instructions.
+MachineInstr *
+ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
+ switch (MI->getOpcode()) {
+ case ARM::MOVCCr:
+ case ARM::t2MOVCCr: {
+ // MOVCC can be commuted by inverting the condition.
+ unsigned PredReg = 0;
+ ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
+ // MOVCC AL can't be inverted. Shouldn't happen.
+ if (CC == ARMCC::AL || PredReg != ARM::CPSR)
+ return NULL;
+ MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
+ if (!MI)
+ return NULL;
+ // After swapping the MOVCC operands, also invert the condition.
+ MI->getOperand(MI->findFirstPredOperandIdx())
+ .setImm(ARMCC::getOppositeCondition(CC));
+ return MI;
+ }
+ }
+ return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
+}
/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
/// instruction is encoded with an 'S' bit is determined by the optional CPSR
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Wed Apr 4 13:23:42 2012
@@ -139,6 +139,8 @@
MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
+ MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
+
virtual bool produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Apr 4 13:23:42 2012
@@ -4044,10 +4044,13 @@
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in {
+
+let isCommutable = 1 in
def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4, IIC_iCMOVr,
[/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">;
+
def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, so_reg_imm:$shift, pred:$p),
4, IIC_iCMOVsr,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Apr 4 13:23:42 2012
@@ -2872,6 +2872,8 @@
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in {
+
+let isCommutable = 1 in
def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
(ins rGPR:$false, rGPR:$Rm, pred:$p),
4, IIC_iCMOVr,
Modified: llvm/trunk/lib/Target/ARM/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/README.txt (original)
+++ llvm/trunk/lib/Target/ARM/README.txt Wed Apr 4 13:23:42 2012
@@ -501,11 +501,6 @@
//===---------------------------------------------------------------------===//
-ARM::MOVCCr is commutable (by flipping the condition). But we need to implement
-ARMInstrInfo::commuteInstruction() to support it.
-
-//===---------------------------------------------------------------------===//
-
Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting
LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg)
Added: llvm/trunk/test/CodeGen/ARM/commute-movcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/commute-movcc.ll?rev=154033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/commute-movcc.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/commute-movcc.ll Wed Apr 4 13:23:42 2012
@@ -0,0 +1,63 @@
+; RUN: llc -mtriple=thumbv7-apple-ios -disable-code-place < %s | FileCheck %s
+; RUN: llc -mtriple=armv7-apple-ios -disable-code-place < %s | FileCheck %s
+
+; LLVM IR optimizers canonicalize icmp+select this way.
+; Make sure that TwoAddressInstructionPass can commute the corresponding
+; MOVCC instructions to avoid excessive copies in one of the if blocks.
+;
+; CHECK: %if.then
+; CHECK-NOT: mov
+; CHECK: movlo
+; CHECK: movlo
+; CHECK-NOT: mov
+
+; CHECK: %if.else
+; CHECK-NOT: mov
+; CHECK: movls
+; CHECK: movls
+; CHECK-NOT: mov
+
+; CHECK: %if.end8
+
+define i32 @f(i32* nocapture %a, i32 %Pref) nounwind ssp {
+entry:
+ br label %for.body
+
+for.body: ; preds = %entry, %if.end8
+ %i.012 = phi i32 [ 0, %entry ], [ %inc, %if.end8 ]
+ %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ]
+ %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ]
+ %arrayidx = getelementptr inbounds i32* %a, i32 %i.012
+ %0 = load i32* %arrayidx, align 4, !tbaa !0
+ %mul = mul i32 %0, %0
+ %sub = add nsw i32 %i.012, -5
+ %cmp2 = icmp eq i32 %sub, %Pref
+ br i1 %cmp2, label %if.else, label %if.then
+
+if.then: ; preds = %for.body
+ %cmp3 = icmp ult i32 %mul, %BestCost.011
+ %i.0.BestIdx.0 = select i1 %cmp3, i32 %i.012, i32 %BestIdx.010
+ %mul.BestCost.0 = select i1 %cmp3, i32 %mul, i32 %BestCost.011
+ br label %if.end8
+
+if.else: ; preds = %for.body
+ %cmp5 = icmp ugt i32 %mul, %BestCost.011
+ %BestIdx.0.i.0 = select i1 %cmp5, i32 %BestIdx.010, i32 %i.012
+ %BestCost.0.mul = select i1 %cmp5, i32 %BestCost.011, i32 %mul
+ br label %if.end8
+
+if.end8: ; preds = %if.else, %if.then
+ %BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ]
+ %BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ]
+ store i32 %mul, i32* %arrayidx, align 4, !tbaa !0
+ %inc = add i32 %i.012, 1
+ %cmp = icmp eq i32 %inc, 11
+ br i1 %cmp, label %for.end, label %for.body
+
+for.end: ; preds = %if.end8
+ ret i32 %BestIdx.1
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
Modified: llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/machine-cse-cmp.ll Wed Apr 4 13:23:42 2012
@@ -10,7 +10,7 @@
; CHECK: cmp
; CHECK: moveq
; CHECK-NOT: cmp
-; CHECK: moveq
+; CHECK: mov{{eq|ne}}
%tmp1 = icmp eq i32 %cond1, 0
%tmp2 = select i1 %tmp1, i32 %x1, i32 %x2
%tmp3 = select i1 %tmp1, i32 %x2, i32 %x3
Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=154033&r1=154032&r2=154033&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Wed Apr 4 13:23:42 2012
@@ -64,7 +64,7 @@
entry:
; ARM: t4:
; ARM: ldr
-; ARM: movlt
+; ARM: mov{{lt|ge}}
; ARMT2: t4:
; ARMT2: movwlt [[R0:r[0-9]+]], #65365
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