[llvm-commits] Register allocation in ascending order

[Shamil Kurmangaleev]

Hi Jakob,
Thanks for the commit, it has resolved our issues.
This case is not uncommon, copying of structures that is implemented
with memcpy and memcpy on ARM is always lowered into the series of ldr
and str with some set of equal live intervals.  In our tests there is no
code scheduled between ldr/str usually, but I'm not sure in general.

Thanks,
 Shamil Kurmangaleev


On 04/03/2012 02:37 AM, Jakob Stoklund Olesen wrote:
> On Apr 2, 2012, at 7:35 AM, Shamil Kurmangaleev <kursh at ispras.ru> wrote:
>
>> This is a patch for the greedy register allocator that makes possible to
>> allocate registers in ascending order.
>> It simply sorts the equal live intervals by their start index and after
>> this the register allocation for this live interval happens in the order
>> defined in Tablegen.
> Hi Shamil,
>
> I committed a slightly simplified version of your patch in r153904. Thanks!
>
> /jakob
>