[llvm-commits] [llvm] r153904 - in /llvm/trunk: lib/CodeGen/RegAllocGreedy.cpp test/CodeGen/ARM/ldrd.ll test/CodeGen/ARM/reg_asc_order.ll test/CodeGen/ARM/select.ll test/CodeGen/X86/store_op_load_fold2.ll test/CodeGen/X86/vec_shuffle-37.ll
Jakob Stoklund Olesen
stoklund at 2pi.dk
Mon Apr 2 15:30:40 PDT 2012
Author: stoklund
Date: Mon Apr 2 17:30:39 2012
New Revision: 153904
URL: http://llvm.org/viewvc/llvm-project?rev=153904&view=rev
Log:
Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.
Patch by Shamil Kurmangaleev!
Added:
llvm/trunk/test/CodeGen/ARM/reg_asc_order.ll
Modified:
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
llvm/trunk/test/CodeGen/ARM/ldrd.ll
llvm/trunk/test/CodeGen/ARM/select.ll
llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=153904&r1=153903&r2=153904&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Apr 2 17:30:39 2012
@@ -428,13 +428,13 @@
Prio |= (1u << 30);
}
- Queue.push(std::make_pair(Prio, Reg));
+ Queue.push(std::make_pair(Prio, ~Reg));
}
LiveInterval *RAGreedy::dequeue() {
if (Queue.empty())
return 0;
- LiveInterval *LI = &LIS->getInterval(Queue.top().second);
+ LiveInterval *LI = &LIS->getInterval(~Queue.top().second);
Queue.pop();
return LI;
}
Modified: llvm/trunk/test/CodeGen/ARM/ldrd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ldrd.ll?rev=153904&r1=153903&r2=153904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ldrd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ldrd.ll Mon Apr 2 17:30:39 2012
@@ -44,8 +44,7 @@
; BASIC: str
; GREEDY: @f
; GREEDY: %bb
-; GREEDY: ldr
-; GREEDY: ldr
+; GREEDY: ldrd
; GREEDY: str
define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind {
entry:
Added: llvm/trunk/test/CodeGen/ARM/reg_asc_order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_asc_order.ll?rev=153904&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/reg_asc_order.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/reg_asc_order.ll Mon Apr 2 17:30:39 2012
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; Check that memcpy gets lowered to ldm/stm, at least in this very smple case.
+
+%struct.Foo = type { i32, i32, i32, i32 }
+
+define void @_Z10CopyStructP3FooS0_(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
+entry:
+;CHECK: ldm
+;CHECK: stm
+ %0 = bitcast %struct.Foo* %a to i8*
+ %1 = bitcast %struct.Foo* %b to i8*
+ tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 16, i32 4, i1 false)
+ ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
Modified: llvm/trunk/test/CodeGen/ARM/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=153904&r1=153903&r2=153904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select.ll Mon Apr 2 17:30:39 2012
@@ -76,12 +76,12 @@
; block generated, odds are good that we have close to the ideal code for this:
;
; CHECK-NEON: _f8:
-; CHECK-NEON: adr r2, LCPI7_0
-; CHECK-NEON-NEXT: movw r3, #1123
-; CHECK-NEON-NEXT: adds r1, r2, #4
-; CHECK-NEON-NEXT: cmp r0, r3
+; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
+; CHECK-NEON-NEXT: movw [[R3:r[0-9]+]], #1123
+; CHECK-NEON-NEXT: adds {{r.*}}, [[R2]], #4
+; CHECK-NEON-NEXT: cmp r0, [[R3]]
; CHECK-NEON-NEXT: it ne
-; CHECK-NEON-NEXT: movne r1, r2
+; CHECK-NEON-NEXT: movne {{r.*}}, [[R2]]
; CHECK-NEON-NEXT: ldr
; CHECK-NEON: bx
Modified: llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll?rev=153904&r1=153903&r2=153904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/store_op_load_fold2.ll Mon Apr 2 17:30:39 2012
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s
+; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=att | FileCheck %s -check-prefix=ATT
+; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s -check-prefix=INTEL
target datalayout = "e-p:32:32"
%struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
@@ -16,9 +17,14 @@
store i64 %tmp2676.us.us, i64* %tmp2666
ret i32 0
-; CHECK: and {{E..}}, DWORD PTR [360]
-; CHECK: and DWORD PTR [356], {{E..}}
-; CHECK: mov DWORD PTR [360], {{E..}}
+; INTEL: and {{E..}}, DWORD PTR [360]
+; INTEL: and DWORD PTR [356], {{E..}}
+; FIXME: mov DWORD PTR [360], {{E..}}
+; The above line comes out as 'mov 360, EAX', but when the register is ECX it works?
+
+; ATT: andl 360, %{{e..}}
+; ATT: andl %{{e..}}, 356
+; ATT: movl %{{e..}}, 360
}
Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=153904&r1=153903&r2=153904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Mon Apr 2 17:30:39 2012
@@ -4,10 +4,10 @@
define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp {
entry:
-; CHECK: movaps ({{%rdi|%rcx}}), %xmm0
-; CHECK: movaps %xmm0, %xmm1
-; CHECK-NEXT: movss %xmm2, %xmm1
-; CHECK-NEXT: shufps $36, %xmm1, %xmm0
+; CHECK: movaps ({{%rdi|%rcx}}), %[[XMM0:xmm[0-9]+]]
+; CHECK: movaps %[[XMM0]], %[[XMM1:xmm[0-9]+]]
+; CHECK-NEXT: movss %xmm{{[0-9]+}}, %[[XMM1]]
+; CHECK-NEXT: shufps $36, %[[XMM1]], %[[XMM0]]
%0 = load <4 x i32>* undef, align 16
%1 = load <4 x i32>* %a0, align 16
%2 = shufflevector <4 x i32> %1, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
More information about the llvm-commits
mailing list