[llvm-commits] [llvm] r153876 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

[Roman Divacky]

Author: rdivacky
Date: Mon Apr  2 10:49:30 2012
New Revision: 153876

URL: http://llvm.org/viewvc/llvm-project?rev=153876&view=rev
Log:
Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=153876&r1=153875&r2=153876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr  2 10:49:30 2012
@@ -446,7 +446,16 @@
   // Darwin passes everything on 4 byte boundary.
   if (TM.getSubtarget<PPCSubtarget>().isDarwin())
     return 4;
-  // FIXME SVR4 TBD
+
+  // 16byte and wider vectors are passed on 16byte boundary.
+  if (VectorType *VTy = dyn_cast<VectorType>(Ty))
+    if (VTy->getBitWidth() >= 128)
+      return 16;
+
+  // The rest is 8 on PPC64 and 4 on PPC32 boundary.
+   if (PPCSubTarget.isPPC64())
+     return 8;
+
   return 4;
 }