[llvm-commits] Register allocation in ascending order

[Shamil Kurmangaleev]

Hello,

This is a patch for the greedy register allocator that makes possible to
allocate registers in ascending order.
It simply sorts the equal live intervals by their start index and after
this the register allocation for this live interval happens in the order
defined in Tablegen.

The motivation for this patch is that on ARM structure copying for the
following struct:

%struct.Foo = type { i32, i32, i32, i32 }

define void @_Z10CopyStructP3FooS0_(%struct.Foo* nocapture %a,
%struct.Foo* nocapture %b) nounwind {
entry:
   %0 = bitcast %struct.Foo* %a to i8*
   %1 = bitcast %struct.Foo* %b to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 16, i32
4, i1 false)
   ret void
}

will be generated as:

         ldr     r12, [r1]
         ldr     r3, [r1, #4]
         ldr     r2, [r1, #8]
         ldr     r1, [r1, 12]
         str     r12, [r0]
         str     r3, [r0, #4]
         str     r2, [r0, #8]
         str     r1, [r0, #12]

After the patch we will see:

         ldm     r1, {r2, r3, r12}
         ldr     r1, [r1, #12]
         stm     r0, {r2, r3, r12}
         str     r1, [r0, #12]
         bx      lr


The patch results from the work sponsored by Samsung.

Thanks,
Shamil Kurmangaleev


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