[llvm-commits] [llvm] r153850 - /llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
Hal Finkel
hfinkel at anl.gov
Sun Apr 1 13:08:08 PDT 2012
Author: hfinkel
Date: Sun Apr 1 15:08:08 2012
New Revision: 153850
URL: http://llvm.org/viewvc/llvm-project?rev=153850&view=rev
Log:
Add LdStSTD* itin. for the PPC64 A2 core.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td?rev=153850&r1=153849&r2=153850&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td Sun Apr 1 15:08:08 2012
@@ -350,6 +350,26 @@
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
[26, 7],
[NoBypass, GPR_Bypass]>,
+ InstrItinData<LdStSTD , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
+ InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
+ IU4_4, IU4_5, IU4_6, IU4_7]>,
+ InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
+ InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
+ InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
+ InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
+ InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
+ [13, 7],
+ [GPR_Bypass, GPR_Bypass]>,
+ InstrItinData<LdStSTDCX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
+ InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
+ IU4_4, IU4_5, IU4_6, IU4_7]>,
+ InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
+ InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
+ InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
+ InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
+ InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
+ [26, 7],
+ [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTWCX , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
IU4_4, IU4_5, IU4_6, IU4_7]>,
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