[llvm-commits] Fix bug 11753 - Incorrect code generated for 64bit types on ARM

[Sandeep Patel]

You're testing apcs-gnu, but referring to the aapcs spec.

i64 parameter alignment should already be handled by the CCIfAlign<>
parts of ARMCallingConv.td in the backend for AAPCS.

deep

On Thu, Mar 29, 2012 at 9:22 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:
> Hello,
>
>
>
> This is a bug fix for Clang. It fixes bug 11753 - Incorrect code generated
> for 64bit types on ARM.
>
>
>
> ARM calling convention requires a double-word sized type is passed in
> two consecutive registers (r0,r1 or r2,r3). (See
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf
> 5.1.1.1, page 16).
>
>
>
> However, currently, for apcs-gnu ABI, such constraint has not been
> implemented.
>
>
>
> This patch fixes this issue by padding a register if needed. This solution
> is similar to a recent fix for MIPS.
>
>
>
> I’m attaching my patch
> (0001-Fix-the-missed-register-padding-for-passing-long-lon.patch), a new
> unit test case (0002-unnit-test.patch), as well as the running results of
> unit test (unit_test_after.txt) and the test suite
> (testsuite.report.simple.txt).  My patch doesn’t cause any errors.
>
>
>
> I also uploaded the same files to the bugzilla.
>
>
>
> Please kindly review the codes.
>
>
>
> Thanks,
>
> Weiming
>
>
>
>
>
>
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