[llvm-commits] Fix for disassembling unpredictable arithmetic/adc/sbc instructions fon ARM

[Silviu Baranga]

Hi,

 

Here are two patches that make the disassembler 

emit warnings when decoding some unpredictable 

instructions on ARM. Previously the disassembler

would emit errors or accept these instructions as

being predictable.

 

This is done by changing some register classes 

to not allow the pc operand, and by specifying

the unpredictable bit fields.

 

AAI.diff : The patch affects arithmetic instructions,

   modifies and renames the 'invalid-LDRT-arm.txt' 

   test  to 'unpredictable-SHADD16-arm.txt' because

   it actually decodes an unpredictable shadd16

   instruction. 

adc.diff:  This patch affects the adc/sbc instructions.

  It also adds a regression test.

 

Please review.

 

Thanks,

Silviu
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20120328/53b058b0/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: AAI.diff
Type: application/octet-stream
Size: 2374 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20120328/53b058b0/attachment.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: adc.diff
Type: application/octet-stream
Size: 1996 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20120328/53b058b0/attachment-0001.obj>