[llvm-commits] [dragonegg] r153505 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp

Duncan Sands baldrick at free.fr
Tue Mar 27 03:34:28 PDT 2012


Author: baldrick
Date: Tue Mar 27 05:34:28 2012
New Revision: 153505

URL: http://llvm.org/viewvc/llvm-project?rev=153505&view=rev
Log:
VEC_EXTRACT_EVEN_EXPR, VEC_EXTRACT_ODD_EXPR, VEC_INTERLEAVE_HIGH_EXPR and
VEC_INTERLEAVE_LOW_EXPR were removed in gcc-4.7 in favour of VEC_PERM_EXPR.
Note that this doesn't add support for VEC_PERM_EXPR.

Modified:
    dragonegg/trunk/include/dragonegg/Internals.h
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/include/dragonegg/Internals.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=153505&r1=153504&r2=153505&view=diff
==============================================================================
--- dragonegg/trunk/include/dragonegg/Internals.h (original)
+++ dragonegg/trunk/include/dragonegg/Internals.h Tue Mar 27 05:34:28 2012
@@ -563,10 +563,12 @@
   Value *EmitReg_ROUND_DIV_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_TRUNC_DIV_EXPR(tree_node *op0, tree_node *op1, bool isExact);
   Value *EmitReg_TRUNC_MOD_EXPR(tree_node *op0, tree_node *op1);
+#if (GCC_MINOR < 7)
   Value *EmitReg_VEC_EXTRACT_EVEN_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_VEC_EXTRACT_ODD_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_VEC_INTERLEAVE_HIGH_EXPR(tree_node *op0, tree_node *op1);
   Value *EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree_node *op0, tree_node *op1);
+#endif
   Value *EmitReg_VEC_PACK_TRUNC_EXPR(tree_node *type, tree_node *op0,
                                      tree_node *op1);
   Value *EmitReg_VEC_WIDEN_MULT_HI_EXPR(tree_node *type, tree_node *op0,

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=153505&r1=153504&r2=153505&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Tue Mar 27 05:34:28 2012
@@ -7437,6 +7437,7 @@
     Builder.CreateURem(LHS, RHS) : Builder.CreateSRem(LHS, RHS);
 }
 
+#if (GCC_MINOR < 7)
 Value *TreeToLLVM::EmitReg_VEC_EXTRACT_EVEN_EXPR(tree op0, tree op1) {
   Value *LHS = EmitRegister(op0);
   Value *RHS = EmitRegister(op1);
@@ -7447,7 +7448,9 @@
     Mask.push_back(Builder.getInt32(2*i));
   return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
 }
+#endif
 
+#if (GCC_MINOR < 7)
 Value *TreeToLLVM::EmitReg_VEC_EXTRACT_ODD_EXPR(tree op0, tree op1) {
   Value *LHS = EmitRegister(op0);
   Value *RHS = EmitRegister(op1);
@@ -7458,7 +7461,9 @@
     Mask.push_back(Builder.getInt32(2*i+1));
   return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
 }
+#endif
 
+#if (GCC_MINOR < 7)
 Value *TreeToLLVM::EmitReg_VEC_INTERLEAVE_HIGH_EXPR(tree op0, tree op1) {
   Value *LHS = EmitRegister(op0);
   Value *RHS = EmitRegister(op1);
@@ -7472,7 +7477,9 @@
   }
   return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
 }
+#endif
 
+#if (GCC_MINOR < 7)
 Value *TreeToLLVM::EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree op0, tree op1) {
   Value *LHS = EmitRegister(op0);
   Value *RHS = EmitRegister(op1);
@@ -7486,6 +7493,7 @@
   }
   return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
 }
+#endif
 
 Value *TreeToLLVM::EmitReg_VEC_PACK_TRUNC_EXPR(tree type, tree op0, tree op1) {
   // Eg: <4 x float> = VEC_PACK_TRUNC_EXPR(<2 x double>, <2 x double>).
@@ -8532,6 +8540,7 @@
     RHS = EmitReg_TruthOp(type, rhs1, rhs2, Instruction::Or); break;
   case TRUTH_XOR_EXPR:
     RHS = EmitReg_TruthOp(type, rhs1, rhs2, Instruction::Xor); break;
+#if (GCC_MINOR < 7)
   case VEC_EXTRACT_EVEN_EXPR:
     RHS = EmitReg_VEC_EXTRACT_EVEN_EXPR(rhs1, rhs2); break;
   case VEC_EXTRACT_ODD_EXPR:
@@ -8540,6 +8549,7 @@
     RHS = EmitReg_VEC_INTERLEAVE_HIGH_EXPR(rhs1, rhs2); break;
   case VEC_INTERLEAVE_LOW_EXPR:
     RHS = EmitReg_VEC_INTERLEAVE_LOW_EXPR(rhs1, rhs2); break;
+#endif
   case VEC_LSHIFT_EXPR:
     RHS = EmitReg_VecShiftOp(rhs1, rhs2, /*isLeftShift*/true); break;
   case VEC_PACK_TRUNC_EXPR:





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