[llvm-commits] [llvm] r153135 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb2.td
Chad Rosier
mcrosier at apple.com
Tue Mar 20 14:59:37 PDT 2012
On Mar 20, 2012, at 2:51 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Tue, Mar 20, 2012 at 2:28 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>> Author: evancheng
>> Date: Tue Mar 20 16:28:05 2012
>> New Revision: 153135
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=153135&view=rev
>> Log:
>> Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
>
> This change is causing CodeGen/ARM/select_xform.ll to fail
Should be fixed in revision 153140. Evan, please make sure this is the proper fix.
> -Eli
>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=153135&r1=153134&r2=153135&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Mar 20 16:28:05 2012
>> @@ -4085,74 +4085,43 @@
>> [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
>> RegConstraint<"$false = $Rd">;
>>
>> -let isCodeGenOnly = 1 in {
>> // Conditional instructions
>> -multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
>> - InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
>> - def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
>> - iii, opc, "\t$Rd, $Rn, $imm", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - bits<4> Rd;
>> - bits<4> Rn;
>> - bits<12> imm;
>> - let Inst{25} = 1;
>> - let Inst{19-16} = Rn;
>> - let Inst{15-12} = Rd;
>> - let Inst{11-0} = imm;
>> - }
>> - def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
>> - iir, opc, "\t$Rd, $Rn, $Rm", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - bits<4> Rd;
>> - bits<4> Rn;
>> - bits<4> Rm;
>> - let Inst{25} = 0;
>> - let Inst{19-16} = Rn;
>> - let Inst{15-12} = Rd;
>> - let Inst{11-4} = 0b00000000;
>> - let Inst{3-0} = Rm;
>> - }
>> -
>> - def rsi : AsI1<opcod, (outs GPR:$Rd),
>> - (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
>> - iis, opc, "\t$Rd, $Rn, $shift", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - bits<4> Rd;
>> - bits<4> Rn;
>> - bits<12> shift;
>> - let Inst{25} = 0;
>> - let Inst{19-16} = Rn;
>> - let Inst{15-12} = Rd;
>> - let Inst{11-5} = shift{11-5};
>> - let Inst{4} = 0;
>> - let Inst{3-0} = shift{3-0};
>> - }
>> +multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
>> + Instruction irsr,
>> + InstrItinClass iii, InstrItinClass iir,
>> + InstrItinClass iis> {
>> + def ri : ARMPseudoExpand<(outs GPR:$Rd),
>> + (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
>> + 4, iii, [],
>> + (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> + def rr : ARMPseudoExpand<(outs GPR:$Rd),
>> + (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
>> + 4, iir, [],
>> + (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> + def rsi : ARMPseudoExpand<(outs GPR:$Rd),
>> + (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
>> + 4, iis, [],
>> + (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> + def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
>> + (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
>> + 4, iis, [],
>> + (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> +}
>> +
>> +defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>> +defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>> +defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>>
>> - def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
>> - (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
>> - iis, opc, "\t$Rd, $Rn, $shift", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - bits<4> Rd;
>> - bits<4> Rn;
>> - bits<12> shift;
>> - let Inst{25} = 0;
>> - let Inst{19-16} = Rn;
>> - let Inst{15-12} = Rd;
>> - let Inst{11-8} = shift{11-8};
>> - let Inst{7} = 0;
>> - let Inst{6-5} = shift{6-5};
>> - let Inst{4} = 1;
>> - let Inst{3-0} = shift{3-0};
>> - }
>> -} // AsI1_bincc_irs
>> -
>> -defm ANDCC : AsI1_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>> -defm ORRCC : AsI1_bincc_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>> -defm EORCC : AsI1_bincc_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
>> -
>> -} // isCodeGenOnly
>> } // neverHasSideEffects
>>
>> +
>> //===----------------------------------------------------------------------===//
>> // Atomic operations intrinsics
>> //
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=153135&r1=153134&r2=153135&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Mar 20 16:28:05 2012
>> @@ -2952,45 +2952,36 @@
>> (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
>> IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
>> RegConstraint<"$false = $Rd">;
>> +} // isCodeGenOnly = 1
>>
>> -multiclass T2I_bincc_irs<bits<4> opcod, string opc,
>> +multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
>> InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
>> // shifted imm
>> - def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
>> - iii, opc, ".w\t$Rd, $Rn, $imm", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - let Inst{31-27} = 0b11110;
>> - let Inst{25} = 0;
>> - let Inst{24-21} = opcod;
>> - let Inst{15} = 0;
>> - }
>> + def ri : t2PseudoExpand<(outs rGPR:$Rd),
>> + (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s),
>> + 4, iii, [],
>> + (iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> // register
>> - def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
>> - iir, opc, ".w\t$Rd, $Rn, $Rm", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - let Inst{31-27} = 0b11101;
>> - let Inst{26-25} = 0b01;
>> - let Inst{24-21} = opcod;
>> - let Inst{14-12} = 0b000; // imm3
>> - let Inst{7-6} = 0b00; // imm2
>> - let Inst{5-4} = 0b00; // type
>> - }
>> + def rr : t2PseudoExpand<(outs rGPR:$Rd),
>> + (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s),
>> + 4, iir, [],
>> + (irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> // shifted register
>> - def rs : T2sTwoRegShiftedReg<(outs rGPR:$Rd),
>> - (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
>> - iis, opc, ".w\t$Rd, $Rn, $ShiftedRm", []>,
>> - RegConstraint<"$Rn = $Rd"> {
>> - let Inst{31-27} = 0b11101;
>> - let Inst{26-25} = 0b01;
>> - let Inst{24-21} = opcod;
>> - }
>> + def rs : t2PseudoExpand<(outs rGPR:$Rd),
>> + (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s),
>> + 4, iis, [],
>> + (irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
>> + RegConstraint<"$Rn = $Rd">;
>> } // T2I_bincc_irs
>>
>> -defm t2ANDCC : T2I_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> -defm t2ORRCC : T2I_bincc_irs<0b0010, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> -defm t2EORCC : T2I_bincc_irs<0b0100, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> -
>> -} // isCodeGenOnly = 1
>> +defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> +defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> +defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
>> + IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
>> } // neverHasSideEffects
>>
>> //===----------------------------------------------------------------------===//
>>
>>
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