[llvm-commits] [llvm] r153240 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp

[Hal Finkel]

Author: hfinkel
Date: Thu Mar 22 00:28:19 2012
New Revision: 153240

URL: http://llvm.org/viewvc/llvm-project?rev=153240&view=rev
Log:
PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203.

I don't have a small test case yet, but I'll try to construct one.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=153240&r1=153239&r2=153240&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 22 00:28:19 2012
@@ -554,7 +554,8 @@
   // clear can be encoded.  This is extremely uncommon, because normally you
   // only "std" to a stack slot that is at least 4-byte aligned, but it can
   // happen in invalid code.
-  if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
+  if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
+      (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
     if (isIXAddr)
       Offset >>= 2;    // The actual encoded value has the low two bits zero.
     MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);