[llvm-commits] [llvm] r153250 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt

[Silviu Baranga]

Author: sbaranga
Date: Thu Mar 22 08:14:39 2012
New Revision: 153250

URL: http://llvm.org/viewvc/llvm-project?rev=153250&view=rev
Log:
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=153250&r1=153249&r2=153250&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Mar 22 08:14:39 2012
@@ -3533,19 +3533,20 @@
 //        property. Remove them when it's possible to add those properties
 //        on an individual MachineInstr, not just an instuction description.
 let isCommutable = 1 in {
-def MUL  : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
+def MUL  : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
                    IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
-                   [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
+                   [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
                    Requires<[IsARM, HasV6]> {
   let Inst{15-12} = 0b0000;
+  let Unpredictable{15-12} = 0b1111;
 }
 
 let Constraints = "@earlyclobber $Rd" in
-def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
+def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
                                             pred:$p, cc_out:$s),
                           4, IIC_iMUL32,
-                         [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
-                         (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
+                         [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
+                         (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
                         Requires<[IsARM, NoV6]>;
 }
 

Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt?rev=153250&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt Thu Mar 22 08:14:39 2012
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x93 0x12 0x01 0x00 
+0x93 0x12 0x01 0x00
+
+# CHECK: potentially undefined
+# CHECK: 0x92 0x0f 0x01 0x00
+0x92 0x0f 0x01 0x00
+
+# CHECK: potentially undefined
+# CHECK: 0x9f 0x02 0x01 0x00
+0x9f 0x02 0x01 0x00
+
+# CHECK: potentially undefined
+# CHECK: 0x92 0x01 0x0f 0x00
+0x92 0x01 0x0f 0x00