[llvm-commits] [llvm] r153252 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/invalid-LDRD-arm.txt test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt
Silviu Baranga
silviu.baranga at arm.com
Thu Mar 22 07:14:50 PDT 2012
Author: sbaranga
Date: Thu Mar 22 09:14:49 2012
New Revision: 153252
URL: http://llvm.org/viewvc/llvm-project?rev=153252&view=rev
Log:
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
Added:
llvm/trunk/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt
llvm/trunk/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt
Removed:
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=153252&r1=153251&r2=153252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Mar 22 09:14:49 2012
@@ -1536,6 +1536,7 @@
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
unsigned W = fieldFromInstruction32(Insn, 21, 1);
unsigned P = fieldFromInstruction32(Insn, 24, 1);
+ unsigned Rt2 = Rt + 1;
bool writeback = (W == 1) | (P == 0);
@@ -1547,7 +1548,86 @@
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
- if (Rt & 0x1) return MCDisassembler::Fail;
+ if (Rt & 0x1) S = MCDisassembler::SoftFail;
+ break;
+ default:
+ break;
+ }
+ switch (Inst.getOpcode()) {
+ case ARM::STRD:
+ case ARM::STRD_PRE:
+ case ARM::STRD_POST:
+ if (P == 0 && W == 1)
+ S = MCDisassembler::SoftFail;
+
+ if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
+ S = MCDisassembler::SoftFail;
+ if (type && Rm == 15)
+ S = MCDisassembler::SoftFail;
+ if (Rt2 == 15)
+ S = MCDisassembler::SoftFail;
+ if (!type && fieldFromInstruction32(Insn, 8, 4))
+ S = MCDisassembler::SoftFail;
+ break;
+ case ARM::STRH:
+ case ARM::STRH_PRE:
+ case ARM::STRH_POST:
+ if (Rt == 15)
+ S = MCDisassembler::SoftFail;
+ if (writeback && (Rn == 15 || Rn == Rt))
+ S = MCDisassembler::SoftFail;
+ if (!type && Rm == 15)
+ S = MCDisassembler::SoftFail;
+ break;
+ case ARM::LDRD:
+ case ARM::LDRD_PRE:
+ case ARM::LDRD_POST:
+ if (type && Rn == 15){
+ if (Rt2 == 15)
+ S = MCDisassembler::SoftFail;
+ break;
+ }
+ if (P == 0 && W == 1)
+ S = MCDisassembler::SoftFail;
+ if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
+ S = MCDisassembler::SoftFail;
+ if (!type && writeback && Rn == 15)
+ S = MCDisassembler::SoftFail;
+ if (writeback && (Rn == Rt || Rn == Rt2))
+ S = MCDisassembler::SoftFail;
+ break;
+ case ARM::LDRH:
+ case ARM::LDRH_PRE:
+ case ARM::LDRH_POST:
+ if (type && Rn == 15){
+ if (Rt == 15)
+ S = MCDisassembler::SoftFail;
+ break;
+ }
+ if (Rt == 15)
+ S = MCDisassembler::SoftFail;
+ if (!type && Rm == 15)
+ S = MCDisassembler::SoftFail;
+ if (!type && writeback && (Rn == 15 || Rn == Rt))
+ S = MCDisassembler::SoftFail;
+ break;
+ case ARM::LDRSH:
+ case ARM::LDRSH_PRE:
+ case ARM::LDRSH_POST:
+ case ARM::LDRSB:
+ case ARM::LDRSB_PRE:
+ case ARM::LDRSB_POST:
+ if (type && Rn == 15){
+ if (Rt == 15)
+ S = MCDisassembler::SoftFail;
+ break;
+ }
+ if (type && (Rt == 15 || (writeback && Rn == Rt)))
+ S = MCDisassembler::SoftFail;
+ if (!type && (Rt == 15 || Rm == 15))
+ S = MCDisassembler::SoftFail;
+ if (!type && writeback && (Rn == 15 || Rn == Rt))
+ S = MCDisassembler::SoftFail;
break;
default:
break;
Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=153252&r1=153251&r2=153252&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Mar 22 09:14:49 2012
@@ -201,7 +201,7 @@
0x20 0x51 0x17 0xe6
# CHECK: strdeq r2, r3, [r0], -r8
-0xf8 0x24 0x00 0x00
+0xf8 0x20 0x00 0x00
# CHECK: ldrdeq r2, r3, [r0], -r12
0xdc 0x24 0x00 0x00
Removed: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt?rev=153251&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt (removed)
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
-
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.68 LDRD (register)
-# if Rt{0} = 1 then UNDEFINED;
-0xd0 0x10 0x00 0x00
Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt?rev=153252&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt Thu Mar 22 09:14:49 2012
@@ -0,0 +1,16 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0xd1 0xf1 0x5f 0x01
+0xd1 0xf1 0x5f 0x01
+# CHECK: potentially undefined
+# CHECK: 0xf1 0xf1 0x5f 0x01
+0xf1 0xf1 0x5f 0x01
+# CHECK: potentially undefined
+# CHECK: 0xf1 0xf1 0x5f 0x01
+0xf1 0xf1 0x5f 0x01
+# CHECK: potentially undefined
+# CHECK: 0xd1 0xe1 0x4f 0x01
+0xd1 0xe1 0x4f 0x01
+
+
Added: llvm/trunk/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt?rev=153252&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt Thu Mar 22 09:14:49 2012
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
+
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.68 LDRD (register)
+# if Rt{0} = 1 then UNDEFINED;
+
+# CHECK: potentially undefined
+# CHECK: 0xd0 0x10 0x00 0x00
+0xd0 0x10 0x00 0x00
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