[llvm-commits] [PATCH] unpredictable instructions with pc register operand on ARM

Silviu Baranga silbar01 at arm.com
Mon Mar 19 07:12:05 PDT 2012


Hi Jim,

 

Thank you for the review. I've attached a new version of the patch that
updates the tests to use FileCheck.

 

Regards,

Silviu

 

From: Jim Grosbach [mailto:grosbach at apple.com] 
Sent: 16 March 2012 18:39
To: Silviu Baranga
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] unpredictable instructions with pc
register operand on ARM

 

Hi Silviu,

 

I agree this is something we should handle better. Thank you for working on
it! A small comment on the patch:

 

It looks like you're removing the standalone error generating test cases and
moving the encoding checks into the associated "unpredictable" test files.
That's general goodness. I realize this isn't original with you, but since
you're in there, please update the tests to use FileCheck instead of grep.
That will enable the tests to both give more reliable diagnostic feedback
when they fail.

 

Regards,

 Jim

 

On Mar 14, 2012, at 7:01 AM, Silviu Baranga <silbar01 at arm.com> wrote:

 

Hi,

 

A lot of ARM instructions are unpredictable if they have the pc

register as an operand. So far this will cause a fail in the

disassemble, rather than a soft fail.

 

This patch fixes this problem by making the decoder function for

GPRnopc operands return SoftFail when it tries to  decode a pc

register operand. It also modifies the register-shifted register

conditional AND instruction by changing the Rd and Rs operand

types from GPR to GPRnopc, in order to make the behaviour

of the AND instruction undefined when Rd and Rn are pc register

operands.

 

Please review.

 

Thanks,

Silviu

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