[llvm-commits] [llvm] r152895 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

[Andrew Trick]

Author: atrick
Date: Fri Mar 16 00:04:25 2012
New Revision: 152895

URL: http://llvm.org/viewvc/llvm-project?rev=152895&view=rev
Log:
misched: add DAG edges from vreg defs to ExitSU.

These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=152895&r1=152894&r2=152895&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Fri Mar 16 00:04:25 2012
@@ -201,8 +201,10 @@
 
       if (TRI->isPhysicalRegister(Reg))
         Uses[Reg].push_back(&ExitSU);
-      else
+      else {
         assert(!IsPostRA && "Virtual register encountered after regalloc.");
+        addVRegUseDeps(&ExitSU, i);
+      }
     }
   } else {
     // For others, e.g. fallthrough, conditional branch, assume the exit