[llvm-commits] [llvm] r152846 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/AsmParser/x test/CodeGen/ARM/fpcmp-opt.ll test/CodeGen/ARM/fpcmp_ueq.ll test/CodeGen/ARM/ifcvt11.ll test/MC/ARM/simple-fp-encoding.s
Jim Grosbach
grosbach at apple.com
Thu Mar 15 14:34:14 PDT 2012
Author: grosbach
Date: Thu Mar 15 16:34:14 2012
New Revision: 152846
URL: http://llvm.org/viewvc/llvm-project?rev=152846&view=rev
Log:
ARM case-insensitive checking for APSR_nzcv.
rdar://11056591
Added:
llvm/trunk/lib/Target/ARM/AsmParser/x
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll
llvm/trunk/test/CodeGen/ARM/ifcvt11.ll
llvm/trunk/test/MC/ARM/simple-fp-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Mar 15 16:34:14 2012
@@ -1198,7 +1198,7 @@
// to APSR.
let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
- "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
+ "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
// Application level FPSCR -> GPR
let hasSideEffects = 1, Uses = [FPSCR] in
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Mar 15 16:34:14 2012
@@ -3258,7 +3258,8 @@
if (isMClass()) {
// See ARMv6-M 10.1.1
- unsigned FlagsVal = StringSwitch<unsigned>(Mask)
+ std::string Name = Mask.lower();
+ unsigned FlagsVal = StringSwitch<unsigned>(Name)
.Case("apsr", 0)
.Case("iapsr", 1)
.Case("eapsr", 2)
@@ -4432,10 +4433,11 @@
else if (Res == -1) // irrecoverable error
return true;
// If this is VMRS, check for the apsr_nzcv operand.
- if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
+ if (Mnemonic == "vmrs" &&
+ Parser.getTok().getString().equals_lower("apsr_nzcv")) {
S = Parser.getTok().getLoc();
Parser.Lex();
- Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
+ Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
return false;
}
Added: llvm/trunk/lib/Target/ARM/AsmParser/x
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/x?rev=152846&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/x (added)
+++ llvm/trunk/lib/Target/ARM/AsmParser/x Thu Mar 15 16:34:14 2012
@@ -0,0 +1,23 @@
+diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+index af973e8..cbdae2a 100644
+--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
++++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+@@ -3254,7 +3254,8 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ SMLoc S = Parser.getTok().getLoc();
+ const AsmToken &Tok = Parser.getTok();
+ assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
+- StringRef Mask = Tok.getString();
++ std::string MaskStr = Tok.getString().lower();
++ StringRef Mask = MaskStr; // convenience for slice() and such.
+
+ if (isMClass()) {
+ // See ARMv6-M 10.1.1
+@@ -3290,7 +3291,7 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
+ size_t Start = 0, Next = Mask.find('_');
+ StringRef Flags = "";
+- std::string SpecReg = Mask.slice(Start, Next).lower();
++ StringRef SpecReg = Mask.slice(Start, Next);
+ if (Next != StringRef::npos)
+ Flags = Mask.slice(Next+1, Mask.size());
+
Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Thu Mar 15 16:34:14 2012
@@ -9,7 +9,7 @@
; CHECK: vldr [[S0:s[0-9]+]],
; CHECK: vldr [[S1:s[0-9]+]],
; CHECK: vcmpe.f32 [[S1]], [[S0]]
-; CHECK: vmrs apsr_nzcv, fpscr
+; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: beq
%0 = load float* %a
%1 = load float* %b
Modified: llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp_ueq.ll Thu Mar 15 16:34:14 2012
@@ -5,7 +5,7 @@
entry:
; CHECK: f7:
; CHECK: vcmpe.f32
-; CHECK: vmrs apsr_nzcv, fpscr
+; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: movweq
; CHECK-NOT: vmrs
; CHECK: movwvs
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt11.ll?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt11.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt11.ll Thu Mar 15 16:34:14 2012
@@ -18,7 +18,7 @@
bb: ; preds = %bb4, %bb.nph
; CHECK: vcmpe.f64
-; CHECK: vmrs apsr_nzcv, fpscr
+; CHECK: vmrs APSR_nzcv, fpscr
%r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
%n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
%scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0
@@ -33,7 +33,7 @@
; CHECK-NOT: vcmpemi
; CHECK-NOT: vmrsmi
; CHECK: vcmpe.f64
-; CHECK: vmrs apsr_nzcv, fpscr
+; CHECK: vmrs APSR_nzcv, fpscr
%scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2
%6 = load double* %scevgep12, align 4
%7 = fcmp uge double %3, %6
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=152846&r1=152845&r2=152846&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Thu Mar 15 16:34:14 2012
@@ -120,8 +120,10 @@
@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
vnmls.f32 s1, s2, s0
-@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
-@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+@ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
+ vmrs APSR_nzcv, fpscr
vmrs apsr_nzcv, fpscr
fmstat
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