[llvm-commits] [PATCH] unpredictable instructions with pc register operand on ARM

[Silviu Baranga]

Hi,

 

A lot of ARM instructions are unpredictable if they have the pc 

register as an operand. So far this will cause a fail in the

disassemble, rather than a soft fail.

 

This patch fixes this problem by making the decoder function for

GPRnopc operands return SoftFail when it tries to  decode a pc

register operand. It also modifies the register-shifted register

conditional AND instruction by changing the Rd and Rs operand

types from GPR to GPRnopc, in order to make the behaviour

of the AND instruction undefined when Rd and Rn are pc register

operands.

 

Please review.

 

Thanks,

Silviu
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