[llvm-commits] [PATCH] Fix decoding of shift-immediate #32

[Jim Grosbach]

Hi Richard,

MC tries to represent instruction operands with the values that will be encoded into the instruction, not the semantic meaning. The arm backend isnt yet completely consistent about it, but that's the general idea. In this case, that means we should use an mcoperand value of zero, as that's what the encoded value is.

Anything creating an operand value of 32 for this is in error. It's getting away with it because the encoder will just use the low 5 bits, but it's still undesirable to rely on that.

Jim

On Mar 13, 2012, at 11:16 AM, Richard Barton <richard.barton at arm.com> wrote:

> With the patch attached this time! Apologies.
> 
>> Hello reviewers,
>> 
>> An MCInst stores a register-shifted-immediate as 2 operands, a register and an
>> immediate operand describing the shift kind and the shift value. This
>> immediate operand value is encoded as 3 bits for the shift kind, which is an
>> enum type ShiftOpc, and 5 bits for the shift value itself. The assembler
>> creates an MCInst immediate operand with the value #32 for ... lsr #32, whilst
>> the decoder creates an MCInst immediate operand with the value 0 for the
>> equivalent encoding. On the face of it, neither is more right than the other,
>> and crucially the two paths followed by llvm-mc (assemble, encode) and
>> (decode, disassemble) match up in their expectations.
>> 
>> Although it probably does not matter either way, intuitively I think it makes
>> more sense for the decoder to write an MCInst operand describing the shift as
>> [32][lsr] rather than [0][lsr] as the latter is not actually legal.
>> 
>> The attached patch handles this case for the decoder. It also reverts part of
>> r137322, which added special case handling for the old decoder behaviour in
>> the instruction printer.
>> 
>> Please review.
>> 
>> Thanks,
>> 
>> Richard Barton
> <decode_lsr_asr_32.patch>
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