[llvm-commits] Fix decoding of shift-immediate #32

[Richard Barton]

Hello reviewers,

An MCInst stores a register-shifted-immediate as 2 operands, a register and an
immediate operand describing the shift kind and the shift value. This immediate
operand value is encoded as 3 bits for the shift kind, which is an enum type
ShiftOpc, and 5 bits for the shift value itself. The assembler creates an MCInst
immediate operand with the value #32 for ... lsr #32, whilst the decoder creates
an MCInst immediate operand with the value 0 for the equivalent encoding. On the
face of it, neither is more right than the other, and crucially the two paths
followed by llvm-mc (assemble, encode) and (decode, disassemble) match up in
their expectations.

Although it probably does not matter either way, intuitively I think it makes
more sense for the decoder to write an MCInst operand describing the shift as
[32][lsr] rather than [0][lsr] as the latter is not actually legal. 

The attached patch handles this case for the decoder. It also reverts part of
r137322, which added special case handling for the old decoder behaviour in the
instruction printer.

Please review.

Thanks,

Richard Barton