[llvm-commits] [PATCH] in PerformSTORECombine check befor generating node

[Shemer, Anat]

Hi,

I will appreciate if you can review the following patch (I can do the commit).

In X86ISelLowering.cpp in the function PerformSTORECombine() there is the CODE BELOW.
The code first generates a type WideVecVT, then creates a node for this type and only after that checks if WideVecVT is a legal type.
I switched the code so the check is done before the redundant node is created.

    // Create a type on which we perform the shuffle
    EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
            StVT.getScalarType(), NumElems*SizeRatio);

    assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());

    SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
    for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;

    // Can't shuffle using an illegal type
    if (!TLI.isTypeLegal(WideVecVT)) return SDValue();

Regards, Anat



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