[llvm-commits] [llvm] r152256 - in /llvm/trunk/lib/CodeGen: MachineScheduler.cpp PostRASchedulerList.cpp ScheduleDAGInstrs.cpp ScheduleDAGInstrs.h
Andrew Trick
atrick at apple.com
Wed Mar 7 15:00:52 PST 2012
Author: atrick
Date: Wed Mar 7 17:00:52 2012
New Revision: 152256
URL: http://llvm.org/viewvc/llvm-project?rev=152256&view=rev
Log:
misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.
Modified:
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=152256&r1=152255&r2=152256&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Wed Mar 7 17:00:52 2012
@@ -226,7 +226,7 @@
releaseNode(&(*I));
}
- InsertPos = Begin;
+ MachineBasicBlock::iterator InsertPos = Begin;
while (SUnit *SU = pickNode()) {
DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=152256&r1=152255&r2=152256&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Wed Mar 7 17:00:52 2012
@@ -365,8 +365,8 @@
if (AntiDepBreak != NULL) {
unsigned Broken =
- AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
- InsertPosIndex, DbgValues);
+ AntiDepBreak->BreakAntiDependencies(SUnits, Begin, End, EndIndex,
+ DbgValues);
if (Broken != 0) {
// We made changes. Update the dependency graph.
@@ -396,7 +396,7 @@
///
void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
if (AntiDepBreak != NULL)
- AntiDepBreak->Observe(MI, Count, InsertPosIndex);
+ AntiDepBreak->Observe(MI, Count, EndIndex);
}
/// FinishBlock - Clean up register live-range state.
@@ -761,24 +761,24 @@
// EmitSchedule - Emit the machine code in scheduled order.
void SchedulePostRATDList::EmitSchedule() {
- Begin = InsertPos;
+ Begin = End;
// If first instruction was a DBG_VALUE then put it back.
if (FirstDbgValue)
- BB->splice(InsertPos, BB, FirstDbgValue);
+ BB->splice(End, BB, FirstDbgValue);
// Then re-insert them according to the given schedule.
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
if (SUnit *SU = Sequence[i])
- BB->splice(InsertPos, BB, SU->getInstr());
+ BB->splice(End, BB, SU->getInstr());
else
// Null SUnit* is a noop.
- TII->insertNoop(*BB, InsertPos);
+ TII->insertNoop(*BB, End);
// Update the Begin iterator, as the first instruction in the block
// may have been scheduled later.
if (i == 0)
- Begin = prior(InsertPos);
+ Begin = prior(End);
}
// Reinsert any remaining debug_values.
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=152256&r1=152255&r2=152256&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Mar 7 17:00:52 2012
@@ -160,8 +160,8 @@
unsigned endcount) {
BB = bb;
Begin = begin;
- InsertPos = end;
- InsertPosIndex = endcount;
+ End = end;
+ EndIndex = endcount;
// Check to see if the scheduler cares about latencies.
UnitLatencies = forceUnitLatencies();
@@ -184,7 +184,7 @@
/// are too high to be hidden by the branch or when the liveout registers
/// used by instructions in the fallthrough block.
void ScheduleDAGInstrs::addSchedBarrierDeps() {
- MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
+ MachineInstr *ExitMI = End != BB->end() ? &*End : 0;
ExitSU.setInstr(ExitMI);
bool AllDepKnown = ExitMI &&
(ExitMI->isCall() || ExitMI->isBarrier());
@@ -476,7 +476,7 @@
// which is contained within a basic block.
SUnits.reserve(BB->size());
- for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) {
+ for (MachineBasicBlock::iterator I = Begin; I != End; ++I) {
MachineInstr *MI = I;
if (MI->isDebugValue())
continue;
@@ -534,7 +534,7 @@
// Walk the list of instructions, from bottom moving up.
MachineInstr *PrevMI = NULL;
- for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
+ for (MachineBasicBlock::iterator MII = End, MIE = Begin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
if (MI && PrevMI) {
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=152256&r1=152255&r2=152256&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Wed Mar 7 17:00:52 2012
@@ -119,16 +119,14 @@
// The block in which to insert instructions
MachineBasicBlock *BB;
- // The beginning of the range to
- // be scheduled. The range extends
- // to InsertPos.
+ /// The beginning of the range to be scheduled.
MachineBasicBlock::iterator Begin;
- // The position to insert instructions
- MachineBasicBlock::iterator InsertPos;
+ /// The end of the range to be scheduled.
+ MachineBasicBlock::iterator End;
- // The index in BB of InsertPos.
- unsigned InsertPosIndex;
+ /// The index in BB of End.
+ unsigned EndIndex;
/// After calling BuildSchedGraph, each machine instruction in the current
/// scheduling region is mapped to an SUnit.
@@ -239,7 +237,7 @@
MachineBasicBlock::iterator begin() const { return Begin; }
/// end - Return an iterator to the bottom of the current scheduling region.
- MachineBasicBlock::iterator end() const { return InsertPos; }
+ MachineBasicBlock::iterator end() const { return End; }
/// NewSUnit - Creates a new SUnit and return a ptr to it.
///
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