[llvm-commits] [llvm] r152162 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/shifter_operand.ll

Chad Rosier mcrosier at apple.com
Tue Mar 6 15:50:32 PST 2012


For the record, this is for rdar://10700575

 Chad

On Mar 6, 2012, at 3:33 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Tue Mar  6 17:33:32 2012
> New Revision: 152162
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=152162&view=rev
> Log:
> Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
> 
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>    llvm/trunk/test/CodeGen/ARM/shifter_operand.ll
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=152162&r1=152161&r2=152162&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Mar  6 17:33:32 2012
> @@ -6142,8 +6142,7 @@
> 
> /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
> /// uses N as its base pointer and that N may be folded in the load / store
> -/// addressing mode. FIXME: This currently only looks for folding of
> -/// [reg +/- imm] addressing modes.
> +/// addressing mode.
> static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
>                                     SelectionDAG &DAG,
>                                     const TargetLowering &TLI) {
> @@ -6163,15 +6162,19 @@
>   if (N->getOpcode() == ISD::ADD) {
>     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
>     if (Offset)
> +      // [reg +/- imm]
>       AM.BaseOffs = Offset->getSExtValue();
>     else
> -      return false;
> +      // [reg +/- reg]
> +      AM.Scale = 1;
>   } else if (N->getOpcode() == ISD::SUB) {
>     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
>     if (Offset)
> +      // [reg +/- imm]
>       AM.BaseOffs = -Offset->getSExtValue();
>     else
> -      return false;
> +      // [reg +/- reg]
> +      AM.Scale = 1;
>   } else
>     return false;
> 
> 
> Modified: llvm/trunk/test/CodeGen/ARM/shifter_operand.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/shifter_operand.ll?rev=152162&r1=152161&r2=152162&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/shifter_operand.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/shifter_operand.ll Tue Mar  6 17:33:32 2012
> @@ -54,12 +54,16 @@
> define fastcc void @test4(i16 %addr) nounwind {
> entry:
> ; A8: test4:
> -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
> -; A8: str [[REG]], [r0]
> +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
> +; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
> +; A8: str [[REG]], [r0, r1, lsl #2]
> +; A8-NOT: str [[REG]], [r0]
> 
> ; A9: test4:
> -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
> -; A9: str [[REG]], [r0]
> +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
> +; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
> +; A9: str [[REG]], [r0, r1, lsl #2]
> +; A9-NOT: str [[REG]], [r0]
>   %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
>   %1 = bitcast i8* %0 to i32*
>   %2 = sext i16 %addr to i32
> 
> 
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