[llvm-commits] [llvm] r152061 - in /llvm/trunk/lib/Target/ARM: ARMInstrNEON.td AsmParser/ARMAsmParser.cpp

Jim Grosbach grosbach at apple.com
Mon Mar 5 13:09:58 PST 2012


Author: grosbach
Date: Mon Mar  5 15:09:58 2012
New Revision: 152061

URL: http://llvm.org/viewvc/llvm-project?rev=152061&view=rev
Log:
ARM Remove a bit of dead code.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=152061&r1=152060&r2=152061&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar  5 15:09:58 2012
@@ -89,15 +89,6 @@
   let ParserMatchClass = VecListOneDAsmOperand;
 }
 // Register list of two sequential D registers.
-def VecListTwoDAsmOperand : AsmOperandClass {
-  let Name = "VecListTwoD";
-  let ParserMethod = "parseVectorList";
-  let RenderMethod = "addVecListOperands";
-}
-def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
-  let ParserMatchClass = VecListTwoDAsmOperand;
-}
-// FIXME: Replace all VecListTwoD with VecListDPair
 def VecListDPairAsmOperand : AsmOperandClass {
   let Name = "VecListDPair";
   let ParserMethod = "parseVectorList";

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=152061&r1=152060&r2=152061&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Mar  5 15:09:58 2012
@@ -1085,11 +1085,6 @@
     return VectorList.Count == 1;
   }
 
-  bool isVecListTwoD() const {
-    if (!isSingleSpacedVectorList()) return false;
-    return VectorList.Count == 2;
-  }
-
   bool isVecListDPair() const {
     if (!isSingleSpacedVectorList()) return false;
     return (ARMMCRegisterClasses[ARM::DPairRegClassID]





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