[llvm-commits] FW: [llvm][PATCH][Review request] Add SSE itineraries for Atom Scheduling

[Gurd, Preston]

Hal,

Thank you for your question.

Publicly available information on scheduling for Intel processors specifies only latency and throughput (the number of cycles to wait before another instruction of the same type can be started). There is no public information with respect to when inputs are required or on how an instruction proceeds through the pipeline.

I would like to be able to add throughput information to the itineraries, but I do not yet know how to do so. If you or anyone else could suggest how that might be done, it would be much appreciated!

In the meantime, we are contenting ourselves with just using the latency information. Using the Atom latencies which have already been patched into the llvm trunk, we have measured performance improvements of between 5 and 10 per cent in our benchmarks. Adding the SSE itineraries improves performance by an additional 2.5 per cent for our scalar benchmarks.

Preston

-----Original Message-----
From: Hal Finkel [mailto:hfinkel at anl.gov] 
Sent: Monday, February 27, 2012 1:03 PM
To: Gurd, Preston
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] FW: [llvm][PATCH][Review request] Add SSE itineraries for Atom Scheduling

Preston,

Out of curiosity, why have you not included any information in the
itinerary on when inputs are required and when results are available?

 -Hal

On Mon, 27 Feb 2012 15:16:19 +0000
"Gurd, Preston" <preston.gurd at intel.com> wrote:

> Ping...
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu
> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Gurd, Preston
> Sent: Wednesday, February 22, 2012 8:14 PM To: Bill Wendling
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm][PATCH][Review request] Add SSE
> itineraries for Atom Scheduling
> 
> Hello Bill,
> 
> Thank you for having a look at this patch.
> 
> The patch basically adds an itinerary class (whose name is prefixed
> by IIC_) or a group of itinerary classes (prefixed by SSE_) to every
> instruction emitted by X86InstrSSE.td, except for AVX only
> instructions or classes.
> 
> In my original patch, there a few changes to the formatting which
> came about because I undid a change without undoing the change in
> formatting. I have corrected this in the attached updated patch.
> 
> In pretty much all of the rest of the patch, it was often necessary
> to add a newline in the middle of the changed line in order to
> observe the 80 column width rule. If you would like me to provide a
> version of this patch which does not split lines, then please let me
> know and I will do so.
> 
> Thanks,
> 
> Preston
> 
> 
> -----Original Message-----
> From: Bill Wendling [mailto:wendling at apple.com] 
> Sent: Sunday, February 19, 2012 3:17 PM
> To: Gurd, Preston
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm][PATCH][Review request] Add SSE
> itineraries for Atom Scheduling
> 
> Hi Preston,
> 
> It's hard to tease out your actual change from the formatting
> changes. Could you separate them please?
> 
> -bw
> 
> On Feb 17, 2012, at 1:33 PM, Gurd, Preston wrote:
> 
> > The attached patch adds instruction itineraries for the SSE
> > instructions to the instruction scheduler for the Intel Atom. 
> > Please review.
> >  
> > Thanks,
> >  
> > Preston
> >  
> > --
> > Preston Gurd <preston.gurd at intel.com>
> >   Intel Waterloo
> >  
> >  
> >  
> > <atomsse.diff>_______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 



-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory