[llvm-commits] [llvm] r151318 - /llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

[Jim Grosbach]

Author: grosbach
Date: Thu Feb 23 18:53:11 2012
New Revision: 151318

URL: http://llvm.org/viewvc/llvm-project?rev=151318&view=rev
Log:
Make sure the regs are low regs for tMUL size reduction.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=151318&r1=151317&r2=151318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Feb 23 18:53:11 2012
@@ -599,7 +599,12 @@
   unsigned Reg1 = MI->getOperand(1).getReg();
   // t2MUL is "special". The tied source operand is second, not first.
   if (MI->getOpcode() == ARM::t2MUL) {
-    if (Reg0 != MI->getOperand(2).getReg()) {
+    unsigned Reg2 = MI->getOperand(2).getReg();
+    // Early exit if the regs aren't all low regs.
+    if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
+        || !isARMLowRegister(Reg2))
+      return false;
+    if (Reg0 != Reg2) {
       // If the other operand also isn't the same as the destination, we
       // can't reduce.
       if (Reg1 != Reg0)