[llvm-commits] [llvm] r151233 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

[Andrew Trick]

Author: atrick
Date: Wed Feb 22 21:16:24 2012
New Revision: 151233

URL: http://llvm.org/viewvc/llvm-project?rev=151233&view=rev
Log:
misched: cleanup reaching def computation

Ignore undef uses completely.
Use a more explicit SlotIndex API.
Add more explicit comments.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=151233&r1=151232&r2=151233&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Feb 22 21:16:24 2012
@@ -408,10 +408,12 @@
 
   // Lookup this operand's reaching definition.
   assert(LIS && "vreg dependencies requires LiveIntervals");
-  SlotIndex UseIdx = LIS->getSlotIndexes()->getInstructionIndex(MI);
+  SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
   LiveInterval *LI = &LIS->getInterval(Reg);
-  VNInfo *VNI = LI->getVNInfoAt(UseIdx);
+  VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
+  // VNI will be valid because MachineOperand::readsReg() is checked by caller.
   MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
+  // Phis and other noninstructions (after coalescing) have a NULL Def.
   if (Def) {
     SUnit *DefSU = getSUnit(Def);
     if (DefSU) {
@@ -540,7 +542,7 @@
         assert(!IsPostRA && "Virtual register encountered!");
         if (MO.isDef())
           addVRegDefDeps(SU, j);
-        else
+        else if (MO.readsReg()) // ignore undef operands
           addVRegUseDeps(SU, j);
       }
     }