[llvm-commits] [llvm] r151166 - in /llvm/trunk/lib/Target/Hexagon: HexagonAsmPrinter.cpp HexagonInstrInfo.cpp HexagonInstrInfo.td HexagonRegisterInfo.cpp

[Sirish Pande]

Author: sirish
Date: Wed Feb 22 10:45:10 2012
New Revision: 151166

URL: http://llvm.org/viewvc/llvm-project?rev=151166&view=rev
Log:
Efficient pattern for store truncate. Patch by Evandro Menezes.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=151166&r1=151165&r2=151166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Wed Feb 22 10:45:10 2012
@@ -374,19 +374,6 @@
     O << "}";
     }
     printInstruction(MI, O);
-  } else if (MI->getOpcode() == Hexagon::STriwt) {
-    //
-    // Handle truncated store on Hexagon.
-    //
-    O << "\tmemw(";
-    printHexagonMEMriOperand(MI, 0, O);
-
-    O << ") = ";
-    unsigned SubRegNum =
-      TM.getRegisterInfo()->getSubReg(MI->getOperand(2)
-                                      .getReg(), Hexagon::subreg_loreg);
-    const char *SubRegName = getRegisterName(SubRegNum);
-    O << SubRegName << '\n';
   } else if (MI->getOpcode() == Hexagon::MPYI_rin) {
     // Handle multipy with -ve constant on Hexagon:
     // "$dst =- mpyi($src1, #$src2)"

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=151166&r1=151165&r2=151166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Feb 22 10:45:10 2012
@@ -1397,7 +1397,6 @@
 
   case Hexagon::LDriw:
   case Hexagon::STriw:
-  case Hexagon::STriwt:
     assert((Offset % 4 == 0) && "Offset has incorrect alignment");
     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
       (Offset <= Hexagon_MEMW_OFFSET_MAX);

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=151166&r1=151165&r2=151166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Feb 22 10:45:10 2012
@@ -1999,11 +1999,6 @@
             "memw($src1+#$src2) = $src3",
             [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
 
-def STriwt : STInst<(outs),
-            (ins MEMri:$addr, DoubleRegs:$src1),
-            "memw($addr) = $src1",
-            [(truncstorei32 DoubleRegs:$src1, ADDRriS11_2:$addr)]>;
-
 let mayStore = 1, neverHasSideEffects = 1 in
 def STriw_GP : STInst<(outs),
             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
@@ -2745,7 +2740,7 @@
 def :  Pat<(i1 (trunc DoubleRegs:$src)),
        (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
 
-// Map memw(Rs) = Rdd -> memw(Rs) = Rt.
+// Map memb(Rs) = Rdd -> memb(Rs) = Rt.
 def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
       (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
                                                      subreg_loreg)))>;
@@ -2755,6 +2750,11 @@
       (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
                                                      subreg_loreg)))>;
 
+// Map memw(Rs) = Rdd -> memw(Rs) = Rt.
+def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr),
+      (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
+                                                     subreg_loreg)))>;
+
 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
       (STrib ADDRriS11_2:$addr, (TFRI 1))>;

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=151166&r1=151165&r2=151166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Wed Feb 22 10:45:10 2012
@@ -206,8 +206,7 @@
       } else if ((MI.getOpcode() == Hexagon::STriw) ||
                  (MI.getOpcode() == Hexagon::STrid) ||
                  (MI.getOpcode() == Hexagon::STrih) ||
-                 (MI.getOpcode() == Hexagon::STrib) ||
-                 (MI.getOpcode() == Hexagon::STriwt)) {
+                 (MI.getOpcode() == Hexagon::STrib)) {
         // For stores, we need a reserved register. Change
         // memw(r30 + #10000) = r0 to:
         //