[llvm-commits] [llvm] r151136 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

[Andrew Trick]

Author: atrick
Date: Wed Feb 22 00:08:13 2012
New Revision: 151136

URL: http://llvm.org/viewvc/llvm-project?rev=151136&view=rev
Log:
misched: DAG builder should not track dependencies for SSA defs.

The vast majority of virtual register definitions don't need an entry
in the DAG builder's VRegDefs set.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=151136&r1=151135&r2=151136&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Feb 22 00:08:13 2012
@@ -44,7 +44,7 @@
     LoopRegs(MLI, MDT), FirstDbgValue(0) {
   assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
   DbgValues.clear();
-  assert(!(IsPostRA && MF.getRegInfo().getNumVirtRegs()) &&
+  assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
          "Virtual registers must be removed prior to PostRA scheduling");
 }
 
@@ -361,6 +361,10 @@
   const MachineInstr *MI = SU->getInstr();
   unsigned Reg = MI->getOperand(OperIdx).getReg();
 
+  // SSA defs do not have output/anti dependencies.
+  if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
+    return;
+
   // Add output dependence to the next nearest def of this vreg.
   //
   // Unless this definition is dead, the output dependence should be