[llvm-commits] [llvm] r151043 - in /llvm/trunk: include/llvm/MC/MCRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp

[Craig Topper]

Author: ctopper
Date: Tue Feb 21 01:36:39 2012
New Revision: 151043

URL: http://llvm.org/viewvc/llvm-project?rev=151043&view=rev
Log:
Reorder some members in MCRegisterClass to remove padding on 64-bit builds.

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=151043&r1=151042&r2=151043&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Tue Feb 21 01:36:39 2012
@@ -28,14 +28,14 @@
   typedef const unsigned* iterator;
   typedef const unsigned* const_iterator;
 
-  unsigned ID;
+  const unsigned ID;
   const char *Name;
   const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
   const int CopyCost;
   const bool Allocatable;
   const iterator RegsBegin;
-  unsigned RegsSize;
   const unsigned char *const RegSet;
+  const unsigned RegsSize;
   const unsigned RegSetSize;
 
   /// getID() - Return the register class ID number.

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=151043&r1=151042&r2=151043&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Feb 21 01:36:39 2012
@@ -391,8 +391,8 @@
        << RC.SpillAlignment/8 << ", "
        << RC.CopyCost << ", "
        << RC.Allocatable << ", "
-       << RC.getName() << ", " << RC.getOrder().size() << ", "
-       << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits) },\n";
+       << RC.getName() << ", " << RC.getName() << "Bits, "
+       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits) },\n";
   }
 
   OS << "};\n\n";